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 | 2013 | |
|---|---|---|
| j45 |      | Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi: An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter. IEICE Transactions 96-A(2): 434-442 (2013) |
| j44 | | |
| j43 | | Kosuke Mizuno, Kenta Takagi, Yosuke Terachi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto: A Sub-100 mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video. IEICE Transactions 96-C(4): 433-443 (2013) |
| j42 | | Guangji He, Takanobu Sugahara, Yuki Miyamoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 168-mW 2.4X-Real-Time 60-kWord Continuous Speech Recognition Processor VLSI. IEICE Transactions 96-C(4): 444-453 (2013) |
| j41 | | Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto: Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM. IEICE Transactions 96-C(4): 528-537 (2013) |
| j40 | | Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi: A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops. IEICE Transactions 96-C(4): 546-552 (2013) |
| c45 | | Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 40-nm 144-mW VLSI processor for real-time 60-kWord continuous speech recognition. ASP-DAC 2013: 71-72 |
| c44 | | Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique. ASP-DAC 2013: 77-78 |
| c43 | | Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto: A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells. ASP-DAC 2013: 79-80 |
| 2012 | ||
| j39 | | Takashi Matsuda, Shintaro Izumi, Yasuharu Sakai, Takashi Takeuchi, Hidehiro Fujiwara, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto: Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes. IEICE Transactions 95-B(1): 178-188 (2012) |
| j38 | | |
| j37 | | Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto: A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing. IEICE Transactions 95-C(4): 523-533 (2012) |
| j36 | | Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme. IEICE Transactions 95-C(4): 572-578 (2012) |
| j35 | | Shunsuke Okumura, Hidehiro Fujiwara, Kosuke Yamaguchi, Shusuke Yoshimoto, Masahiko Yoshimoto, Hiroshi Kawaguchi: A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme. IEICE Transactions 95-C(4): 579-585 (2012) |
| j34 | | Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Koji Nii, Masahiko Yoshimoto, Hiroshi Kawaguchi: Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process. IEICE Transactions 95-A(8): 1359-1365 (2012) |
| j33 | | Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto: Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure. IEICE Transactions 95-C(10): 1675-1681 (2012) |
| j32 | | Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells. IEICE Transactions 95-A(12): 2226-2233 (2012) |
| j31 | | Guangji He, Takanobu Sugahara, Yuki Miyamoto, Tsuyoshi Fujinaga, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 40 nm 144 mW VLSI Processor for Real-Time 60-kWord Continuous Speech Recognition. IEEE Trans. on Circuits and Systems 59-I(8): 1656-1666 (2012) |
| c42 | | Shinpei Soda, Masahide Nakamura, Shinsuke Matsumoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto: Implementing Virtual Agent as an Interface for Smart Home Voice Control. APSEC 2012: 342-345 |
| c41 |  | Koji Kugata, Shinpei Soda, Yohei Nakata, Shunsuke Okumura, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi: Processor Coupling Architecture for Aggressive Voltage Scaling on Multicores. ARCS Workshops 2012: 375-384 |
| c40 | | Guangji He, Takanobu Sugahara, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 40-nm 168-mW 2.4×-real-time VLSI processor for 60-kWord continuous speech recognition. CICC 2012: 1-4 |
| c39 | | Shinpei Soda, Masahide Nakamura, Shinsuke Matsumoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto: Handsfree Voice Interface for Home Network Service Using a Microphone Array Network. ICNC 2012: 195-200 |
| c38 | | Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto: Neutron-induced soft error rate estimation for SRAM using PHITS. IOLTS 2012: 138-141 |
| c37 | | Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi: A 51-dB SNDR DCO-based TDC using two-stage second-order noise shaping. ISCAS 2012: 3170-3173 |
| c36 | | Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. ISLPED 2012: 85-90 |
| c35 | | Masaharu Terada, Shusuke Yoshimoto, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction. ISQED 2012: 489-492 |
| c34 | | Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Shusuke Yoshimoto, Yohei Nakata, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto: Bit error rate estimation in SRAM considering temperature fluctuation. ISQED 2012: 516-519 |
| c33 | | Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto: Architectural Study of HOG Feature Extraction Processor for Real-Time Object Detection. SiPS 2012: 197-202 |
| 2011 | ||
| j30 | | Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Tsuyoshi Fujinaga, Shintaro Izumi, Yasuo Ariki, Hiroshi Kawaguchi, Masahiko Yoshimoto: A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition. IEICE Transactions 94-C(4): 448-457 (2011) |
| j29 | | Hiroki Noguchi, Kazuo Miura, Tsuyoshi Fujinaga, Takanobu Sugahara, Hiroshi Kawaguchi, Masahiko Yoshimoto: VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000-Word Real-Time Continuous Speech Recognition. IEICE Transactions 94-C(4): 458-467 (2011) |
| j28 | | Toshihiro Konishi, Shintaro Izumi, Koh Tsuruda, Hyeokjong Lee, Takashi Takeuchi, Masahiko Yoshimoto, Hiroshi Kawaguchi: A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio. IEICE Transactions 94-A(11): 2287-2294 (2011) |
| j27 | | Shunsuke Okumura, Yuki Kagiyama, Yohei Nakata, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto: 7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory. IEICE Transactions 94-A(12): 2693-2700 (2011) |
| j26 | | Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Takashi Takeuchi, Masahiko Yoshimoto, Hiroshi Kawaguchi: A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output. IEICE Transactions 94-A(12): 2701-2708 (2011) |
| j25 | | Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi: Data-Intensive Sound Acquisition System with Large-scale Microphone Array. JIP 19: 129-140 (2011) |
| c32 | | Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition. CICC 2011: 1-4 |
| c31 | | Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto: Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy. CICC 2011: 1-4 |
| c30 | | Yohei Nakata, Yukihiro Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto: A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers. DSD 2011: 801-804 |
| c29 | | Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10-19. ESSCIRC 2011: 527-530 |
| c28 | | Shintaro Izumi, Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shinpei Soda, Masahiko Yoshimoto, Hiroshi Kawaguchi: Data Aggregation Protocol for Multiple Sound Sources Acquisition with Microphone Array Network. ICCCN 2011: 1-6 |
| c27 | | Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto: 256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V. ICECS 2011: 524-527 |
| c26 | | Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto: Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS 2011: 151-156 |
| c25 | | Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi: A 40-nm 640-µm2 45-dB opampless all-digital second-order MASH ΔΣ ADC. ISCAS 2011: 518-521 |
| c24 | | Hiroki Noguchi, Shunsuke Okumura, Tomoya Takagi, Koji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi: 0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM. ISQED 2011: 219-222 |
| c23 | | Masahiro Yoshikawa, Shunsuke Okumura, Yohei Nakata, Yuki Kagiyama, Hiroshi Kawaguchi, Masahiko Yoshimoto: Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control. ISQED 2011: 322-325 |
| 2010 | ||
| j24 | | Shintaro Izumi, Takashi Takeuchi, Takashi Matsuda, Hyeokjong Lee, Toshihiro Konishi, Koh Tsuruda, Yasuharu Sakai, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto: A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design. IEICE Transactions 93-C(3): 261-269 (2010) |
| c22 | | Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Masanori Nishino, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 34.7-mW quad-core MIQP solver processor for robot control. CICC 2010: 1-4 |
| c21 | | Shunsuke Okumura, Shusuke Yoshimoto, Kosuke Yamaguchi, Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto: 7T SRAM enabling low-energy simultaneous block copy. CICC 2010: 1-4 |
| c20 | | Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto: Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video. FPL 2010: 608-611 |
| c19 | | Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi: Live demonstration: Intelligent ubiquitous sensor network for sound acquisition. ISCAS 2010: 1413 |
| c18 | | Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi: Intelligent ubiquitous sensor network for sound acquisition. ISCAS 2010: 1414-1417 |
| c17 | | Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Hiroshi Kawaguchi, Masahiko Yoshimoto: Parallel-processing VLSI architecture for mixed integer linear programming. ISCAS 2010: 2362-2365 |
| c16 | | Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto: 0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM. ISLPED 2010: 219-224 |
| 2009 | ||
| j23 | | Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto: A Dependable SRAM with 7T/14T Memory Cells. IEICE Transactions 92-C(4): 423-432 (2009) |
| j22 | | Takashi Takeuchi, Shinji Mikami, Hyeokjong Lee, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto: A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks. IEICE Transactions 92-C(6): 815-821 (2009) |
| c15 | | Tsuyoshi Fujinaga, Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto: Parallelized viterbi processor for 5, 000-word large-vocabulary real-time continuous speech recognition FPGA system. INTERSPEECH 2009: 1483-1486 |
| c14 | | Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. ISQED 2009: 659-663 |
| c13 | | Hiroki Noguchi, Tomoya Takagi, Masahiko Yoshimoto, Hiroshi Kawaguchi: An ultra-low-power VAD hardware implementation for intelligent ubiquitous sensor networks. SiPS 2009: 214-219 |
| c12 | | Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection. VLSI Design 2009: 295-300 |
| 2008 | ||
| j21 | | Yuichiro Murachi, Yuki Fukuyama, Ryo Yamamoto, Junichi Miyakoshi, Hiroshi Kawaguchi, Hajime Ishihara, Masayuki Miyama, Yoshio Matsuda, Masahiko Yoshimoto: A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition. IEICE Transactions 91-C(4): 457-464 (2008) |
| j20 | | Yuichiro Murachi, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto: A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer. IEICE Transactions 91-C(4): 465-478 (2008) |
| j19 | | Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing. IEICE Transactions 91-C(4): 543-552 (2008) |
| j18 | | Takashi Takeuchi, Yu Otake, Masumi Ichien, Akihiro Gion, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto: Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock. IEICE Transactions 91-B(11): 3480-3488 (2008) |
| j17 | | Shintaro Izumi, Takashi Takeuchi, Takashi Matsuda, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto: Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks. IEICE Transactions 91-B(11): 3489-3498 (2008) |
| j16 | | Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto: Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering. IEEE Trans. VLSI Syst. 16(6): 620-627 (2008) |
| c11 | | Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto: A low memory bandwidth Gaussian mixture model (GMM) processor for 20, 000-word real-time speech recognition FPGA system. FPT 2008: 341-344 |
| c10 | | Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto: A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding. ISCAS 2008: 848-851 |
| c9 | | Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto: Quality of a Bit (QoB): A New Concept in Dependable SRAM. ISQED 2008: 98-102 |
| 2007 | ||
| j15 | | Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes. IEICE Transactions 90-C(10): 1949-1956 (2007) |
| j14 | | Augusto Foronda, Yuhi Higuchi, Chikara Ohta, Masahiko Yoshimoto, Yoji Okada: Service Interval Optimization with Delay Bound Guarantee for HCCA in IEEE 802.11e WLANs. IEICE Transactions 90-B(11): 3158-3169 (2007) |
| j13 | | Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme. IEICE Transactions 90-A(12): 2695-2702 (2007) |
| j12 | | Takashi Matsuda, Masumi Ichien, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto: Data Transmission Scheduling Based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks. IEICE Transactions 90-B(12): 3410-3418 (2007) |
| c8 | | Kentaro Kawakami, Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto: Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture. ASP-DAC 2007: 292-297 |
| c7 | | Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing. ISVLSI 2007: 107-112 |
| c6 | | Yuhi Higuchi, Augusto Foronda, Chikara Ohta, Masahiko Yoshimoto, Yoji Okada: Delay Guarantee and Service Interval Optimization for HCCA in IEEE 802.11e WLANs. WCNC 2007: 2080-2085 |
| 2006 | ||
| j11 | | Noriyuki Minegishi, Junichi Miyakoshi, Yuki Kuroda, Tadayoshi Katagiri, Yuki Fukuyama, Ryo Yamamoto, Masayuki Miyama, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto: VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation. IEICE Transactions 89-C(3): 230-242 (2006) |
| j10 | | Shinji Mikami, Takafumi Aonishi, Hironori Yoshino, Chikara Ohta, Hiroshi Kawaguchi, Masahiko Yoshimoto: Aggregation Efficiency-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks. IEICE Transactions 89-B(10): 2741-2751 (2006) |
| j9 | | Junichi Miyakoshi, Yuichiro Murachi, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto: A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing. IEICE Transactions 89-C(11): 1629-1636 (2006) |
| j8 | | Junichi Miyakoshi, Yuichiro Murachi, Tetsuro Matsuno, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masayuki Miyama, Masahiko Yoshimoto: A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture. IEICE Transactions 89-A(12): 3623-3633 (2006) |
| j7 | | Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Kentaro Kawakami, Junichi Miyakoshi, Shinji Mikami, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond. IEICE Transactions 89-A(12): 3634-3641 (2006) |
| j6 | | Kentaro Kawakami, Jun Takemura, Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline. IEICE Transactions 89-A(12): 3642-3651 (2006) |
| c5 | | Takafumi Aonishi, Takashi Matsuda, Shinji Mikami, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto: Impact of Aggregation Efficiency on GIT Routing forWireless Sensor Networks. ICPP Workshops 2006: 151-158 |
| c4 | | Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto: A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. ISLPED 2006: 61-66 |
| c3 | | Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Tetsuro Matsuno: A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing. VLSI-SoC 2006: 192-197 |
| 2005 | ||
| j5 | | Junichi Miyakoshi, Yuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Masayuki Miyama, Masahiko Yoshimoto: A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation. IEICE Transactions 88-C(4): 559-569 (2005) |
| j4 | | Kentaro Kawakami, Miwako Kanamori, Yasuhiro Morita, Jun Takemura, Masayuki Miyama, Masahiko Yoshimoto: Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era. IEICE Transactions 88-A(12): 3290-3297 (2005) |
| j3 | | Yuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Junichi Miyakoshi, Masayuki Miyama, Masahiko Yoshimoto: A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application. IEICE Transactions 88-A(12): 3492-3499 (2005) |
| 2004 | ||
| c2 | | Yuki Kuroda, Junichi Miyakoshi, Masayuki Miyama, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto: A sub-mW MPEG-4 motion estimation processor core for mobile video application. ASP-DAC 2004: 527-528 |
| 2003 | ||
| j2 | | Hideo Ohira, Mitsuru Kodama, Masahiko Yoshimoto: The development and impact on business of the world's first live video streaming distribution platform for 3G mobile videophone terminals. IJEB 1(1): 94-105 (2003) |
| j1 | | Hideo Ohira, Mitsuru Kodama, Masahiko Yoshimoto: A world first development of a multipoint videophone system over 3G-324M protocol. IJMC 1(3): 264-272 (2003) |
| 2001 | ||
| c1 | | A. Watanabe, O. Tooyama, Masayuki Miyama, Masahiko Yoshimoto, J. Akita: An image sensor with fast extraction of objects' positions - rough vision processor. ICIP (2) 2001: 1105-1108 |
Colors in the list of coauthors
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