Qiang Xu

Chuanyu Zhao, Jie Fu, Qiang Xu: Production-ratio oriented optimization for multi-recipe material handling via simultaneous hoist scheduling and production line arrangement. Computers & Chemical Engineering 50: 28-38 (2013)

Tianxing Cai, Sujing Wang, Qiang Xu: Scheduling of multiple chemical plant start-ups to minimize regional air quality impacts. Computers & Chemical Engineering 54: 68-78 (2013)

Chaojun Ouyang, Siming He, Qiang Xu, Yu Luo, Wencheng Zhang: A MacCormack-TVD finite difference method to simulate the mass flow in mountainous terrain with variable computational domain. Computers & Geosciences 52: 1-10 (2013)

Li Jiang, Qiang Xu, Bill Eklow: On Effective Through-Silicon Via Repair for 3-D-Stacked ICs. IEEE Trans. on CAD of Integrated Circuits and Systems 32(4): 559-571 (2013)

Xiao Liu, Qiang Xu: On Multiplexed Signal Tracing for Post-Silicon Validation. IEEE Trans. on CAD of Integrated Circuits and Systems 32(5): 748-759 (2013)

Meiqian Wang, Jian Zhang, Qiang Xu: Optimal design and operation of a C3MR refrigeration system for natural gas liquefaction. Computers & Chemical Engineering 39: 84-95 (2012)

Jie Fu, Tianxing Cai, Qiang Xu: Coupling multiple water-reuse network designs for agile manufacturing. Computers & Chemical Engineering 45: 62-71 (2012)

Zhe Yin, Ziwen Jiang, Qiang Xu: A Discontinuous Finite Volume Method for the Darcy-Stokes Equations. J. Applied Mathematics 2012 (2012)

Xiao Liu, Qiang Xu: On Signal Selection for Visibility Enhancement in Trace-Based Post-Silicon Validation. IEEE Trans. on CAD of Integrated Circuits and Systems 31(8): 1263-1274 (2012)

Xiao Liu, Qiang Xu: On X-Variable Filling and Flipping for Capture-Power Reduction in Linear Decompressor-Based Test Compression Environment. IEEE Trans. on CAD of Integrated Circuits and Systems 31(11): 1743-1753 (2012)

Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. Mak: Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint. IEEE Trans. VLSI Syst. 20(9): 1621-1633 (2012)

Haile Yu, Philip Heng Wai Leong, Qiang Xu: An FPGA Chip Identification Generator Using Configurable Ring Oscillators. IEEE Trans. VLSI Syst. 20(12): 2198-2207 (2012)

Rong Ye, Qiang Xu: Learning-based power management for multi-core processors via idle period manipulation. ASP-DAC 2012: 115-120

Yubin Zhang, Haile Yu, Qiang Xu: CODA: A concurrent online delay measurement architecture for critical paths. ASP-DAC 2012: 169-174

Qiang Xu, Li Jiang, Huiyun Li, Bill Eklow: Yield enhancement for 3D-stacked ICs: Recent advances and challenges. ASP-DAC 2012: 731-737

Feng Yuan, Xiao Liu, Qiang Xu: X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug. DAC 2012: 555-560

Li Jiang, Qiang Xu, Bill Eklow: On effective TSV repair for 3D-stacked ICs. DATE 2012: 793-798

Rong Ye, Feng Yuan, Hai Zhou, Qiang Xu: Clock skew scheduling for timing speculation. DATE 2012: 929-934

Jiancong Fan, Qiang Xu, Yongquan Liang: Analysis of classification learning based on estimation of distribution algorithms. FSKD 2012: 855-859

Jie Zhang, Haile Yu, Qiang Xu: HTOutlier: Hardware Trojan detection with side-channel signature outlier identification. HOST 2012: 55-58

Yuxi Liu, Rong Ye, Feng Yuan, Rakesh Kumar, Qiang Xu: On logic synthesis for timing speculation. ICCAD 2012: 591-596

Xiao Liu, Qiang Xu: On efficient silicon debug with flexible trace interconnection fabric. ITC 2012: 1-9

Yuxi Liu, Qiang Xu: On modeling faults in FinFET logic circuits. ITC 2012: 1-9

Jian Zhang, Qiang Xu: Cascade refrigeration system synthesis based on exergy analysis. Computers & Chemical Engineering 35(9): 1901-1914 (2011)

Chaowei Liu, Jie Fu, Qiang Xu: Simultaneous mixed-integer dynamic optimization for environmentally benign electroplating. Computers & Chemical Engineering 35(11): 2411-2425 (2011)

Bocheng Bao, Zhenghua Ma, Jianping Xu, Zhong Liu, Qiang Xu: A Simple memristor Chaotic Circuit with Complex Dynamics. I. J. Bifurcation and Chaos 21(9): 2629-2645 (2011)

Jiancong Fan, Yongquan Liang, Qiang Xu, Ruisheng Jia, Zhihua Cui: EDA-USL: unsupervised clustering algorithm based on estimation of distribution algorithm. IJWMC 5(1): 88-97 (2011)

Jia Li, Xiao Liu, Yubin Zhang, Yu Hu, Xiaowei Li, Qiang Xu: Capture-power-aware test data compression using selective encoding. Integration 44(3): 205-216 (2011)

Wei Liao, Jurong Ding, Daniele Marinazzo, Qiang Xu, Zhengge Wang, Cuiping Yuan, Zhiqiang Zhang, Guangming Lu, Huafu Chen: Small-world directed networks in the human brain: Multivariate Granger causality analysis of resting-state fMRI. NeuroImage 54(4): 2683-2694 (2011)

Qiang Xu, Qiuwen Chen, Weifeng Li, Jinfeng Ma: Pipe break prediction based on evolutionary data-driven methods with brief recorded data. Rel. Eng. & Sys. Safety 96(8): 942-948 (2011)

Lin Huang, Feng Yuan, Qiang Xu: On Task Allocation and Scheduling for Lifetime Extension of Platform-Based MPSoC Designs. IEEE Trans. Parallel Distrib. Syst. 22(12): 2088-2099 (2011)

Jia Li, Qiang Xu, Dong Xiang: Compression-aware capture power reduction for at-speed testing. ASP-DAC 2011: 806-811

Peter Marwedel, Jürgen Teich, Georgia Kouveli, Iuliana Bacivarov, Lothar Thiele, Soonhoi Ha, Chanhee Lee, Qiang Xu, Lin Huang: Mapping of applications to MPSoCs. CODES+ISSS 2011: 109-118

Yuxi Liu, Feng Yuan, Qiang Xu: Re-synthesis for cost-efficient circuit-level timing speculation. DAC 2011: 158-163

Lin Huang, Rong Ye, Qiang Xu: Customer-aware task allocation and scheduling for multi-mode MPSoCs. DAC 2011: 387-392

Xiao Liu, Qiang Xu: On multiplexed signal tracing for post-silicon debug. DATE 2011: 685-690

Feng Yuan, Xiao Liu, Qiang Xu: On High-Quality Test Pattern Selection and Manipulation. European Test Symposium 2011: 218

Haile Yu, Qiang Xu, Philip Heng Wai Leong: On timing yield improvement for FPGA designs using architectural symmetry (abstract only). FPGA 2011: 278

Haile Yu, Qiang Xu, Philip Heng Wai Leong: On Timing Yield Improvement for FPGA Designs Using Architectural Symmetry. FPL 2011: 539-544

Feng Yuan, Xiao Liu, Qiang Xu: Pseudo-functional testing for small delay defects considering power supply noise effects. ICCAD 2011: 34-39

Rong Ye, Feng Yuan, Qiang Xu: Online clock skew tuning for timing speculation. ICCAD 2011: 442-447

Qiang Xu, Chulin Jiang, Dezheng Liu, Yongxin Pang, Simon Hodgson: Finite element investigation of nano-indentation of coated stainless steel. ICAC 2011: 172-176

Qiang Xu, Mark Wright, Qihua Xu: The development and validation of multi-axial creep damage constitutive equations for P91. ICAC 2011: 177-182

Qiang Xu, Jeffrey Erman, Alexandre Gerber, Zhuoqing Morley Mao, Jeffrey Pang, Shobha Venkataraman: Identifying diverse usage behaviors of smartphone apps. Internet Measurement Conference 2011: 329-344

Qiang Xu, Alexandre Gerber, Zhuoqing Morley Mao, Jeffrey Pang: AccuLoc: practical localization of performance measurements in 3G networks. MobiSys 2011: 183-196

Zhaoguang Wang, Zhiyun Qian, Qiang Xu, Zhuoqing Morley Mao, Ming Zhang: An untold story of middleboxes in cellular networks. SIGCOMM 2011: 374-385

Qiang Xu, Junxian Huang, Zhaoguang Wang, Feng Qian, Alexandre Gerber, Zhuoqing Morley Mao: Cellular data network infrastructure characterization and implication on mobile content placement. SIGMETRICS 2011: 317-328

Chaowei Liu, Jian Zhang, Qiang Xu, Kuyen Li: Cyclic scheduling for best profitability of industrial cracking furnace system. Computers & Chemical Engineering 34(4): 544-554 (2010)

Lin Huang, Qiang Xu: Economic Analysis of Testing Homogeneous Manycore Chips. IEEE Trans. on CAD of Integrated Circuits and Systems 29(8): 1257-1270 (2010)

Lin Huang, Qiang Xu: Lifetime Reliability for Load-Sharing Redundant Systems With Arbitrary Failure Distributions. IEEE Transactions on Reliability 59(2): 319-330 (2010)

Jia Li, Qiang Xu, Yu Hu, Xiaowei Li: X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing. IEEE Trans. VLSI Syst. 18(7): 1081-1092 (2010)

Qiang Xu, Xiao Liu: On signal tracing in post-silicon validation. ASP-DAC 2010: 262-267

Xiao Liu, Qiang Xu: On Signal Tracing for Debugging Speedpath-Related Electrical Errors in Post-Silicon Validation. Asian Test Symposium 2010: 243-248

Lin Huang, Qiang Xu: Performance yield-driven task allocation and scheduling for MPSoCs under process variation. DAC 2010: 326-331

Lin Huang, Qiang Xu: AgeSim: A simulation framework for evaluating the lifetime reliability of processor-based SoCs. DATE 2010: 51-56

Xiao Liu, Yubin Zhang, Feng Yuan, Qiang Xu: Layout-aware pseudo-functional testing for critical paths considering power supply noise effects. DATE 2010: 1432-1437

Lin Huang, Qiang Xu: Energy-efficient task allocation and scheduling for multi-mode MPSoCs under lifetime reliability constraint. DATE 2010: 1584-1589

Haile Yu, Qiang Xu, Philip Heng Wai Leong: Fine-grained characterization of process variation in FPGAs. FPT 2010: 138-145

Haile Yu, Philip Heng Wai Leong, Qiang Xu: An FPGA chip identification generator using configurable ring oscillator. FPT 2010: 312-315

Xiaohua Chen, Qiang Xu: Military Information Grid-based Integrated Photo-electric Detector Technology. GCC 2010: 416-419

Li Jiang, Rong Ye, Qiang Xu: Yield enhancement for 3D-stacked memory by redundancy sharing across dies. ICCAD 2010: 230-234

Feng Yuan, Qiang Xu: On timing-independent false path identification. ICCAD 2010: 532-535

Lin Huang, Qiang Xu: Characterizing the lifetime reliability of manycore processors with core-level redundancy. ICCAD 2010: 680-685

Li Jiang, Yuxi Liu, Lian Duan, Yuan Xie, Qiang Xu: Modeling TSV open defects in 3D-stacked DRAM. ITC 2010: 174-182

Qiang Xu, Jaspal Subhlok, Nathaniel Hammen: Efficient Discovery of Loop Nests in Execution Traces. MASCOTS 2010: 193-202

Junxian Huang, Qiang Xu, Birjodh Tiwana, Zhuoqing Morley Mao, Ming Zhang, Paramvir Bahl: Anatomizing application performance differences on smartphones. MobiSys 2010: 165-178

Dong Xiang, Dianwei Hu, Qiang Xu, Alex Orailoglu: Low-Power Scan Testing for Test Data Compression Using a Routing-Driven Scan Architecture. IEEE Trans. on CAD of Integrated Circuits and Systems 28(7): 1101-1105 (2009)

Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty: SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects. ACM Trans. Design Autom. Electr. Syst. 14(1) (2009)

Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li, Huawei Li: On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems. IEEE Trans. VLSI Syst. 17(9): 1173-1186 (2009)

Yubin Zhang, Lin Huang, Feng Yuan, Qiang Xu: Test Pattern Selection for Potentially Harmful Open Defects in Power Distribution Networks. Asian Test Symposium 2009: 456-461

Xiao Liu, Qiang Xu: Interconnection fabric design for tracing signals in post-silicon validation. DAC 2009: 352-357

Feng Yuan, Qiang Xu: On systematic illegal state identification for pseudo-functional testing. DAC 2009: 702-707

Lin Huang, Feng Yuan, Qiang Xu: Lifetime reliability-aware task allocation and scheduling for MPSoC platforms. DATE 2009: 51-56

Li Jiang, Lin Huang, Qiang Xu: Test architecture design and optimization for three-dimensional SoCs. DATE 2009: 220-225

Xiao Liu, Qiang Xu: Trace signal selection for visibility enhancement in post-silicon validation. DATE 2009: 1338-1343

Xiao Liu, Qiang Xu: A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment. DATE 2009: 1494-1499

Jing Li, Jian-yun Chen, Qiang Xu: The Improved Fuzzy Classification Model on Disaster Loss. FSKD (4) 2009: 409-412

Qiang Xu, Jing Li, Jian-yun Chen: Fuzzy Reliability Analysis of Deep Sliding Plane in Rock Foundation under Dam. FSKD (6) 2009: 525-529

Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. Mak: Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint. ICCAD 2009: 191-196

Qiang Xu, Jaspal Subhlok, Rong Zheng, Sara Voss: Logicalization of communication traces from parallel execution. IISWC 2009: 34-43

Lin Huang, Qiang Xu: Test economics for homogeneous manycore systems. ITC 2009: 1-10

Xiao Liu, Qiang Xu: On simultaneous shift- and capture-power reduction in linear decompressor-based test compression environment. ITC 2009: 1-10

Xiao Liu, Qiang Xu: Trace signal selection for debugging electrical errors in post-silicon validation. ITC 2009: 1

Feng Yuan, Qiang Xu: Compression-aware pseudo-functional testing. ITC 2009: 1-10

Sukhdeep Sodhi, Jaspal Subhlok, Qiang Xu: Performance prediction with skeletons. Cluster Computing 11(2): 151-165 (2008)

Jing-Ling Yang, Qiang Xu: State-Sensitive X-Filling Scheme for Scan Capture Power Reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1338-1343 (2008)

Shan Tang, Qiang Xu: A debug probe for concurrently debugging multiple embedded cores and inter-core transactions in NoC-based systems. ASP-DAC 2008: 416-421

Jia Li, Qiang Xu, Yu Hu, Xiaowei Li: On reducing both shift and capture power for scan-based testing. ASP-DAC 2008: 653-658

Lin Huang, Feng Yuan, Qiang Xu: On reliable modular testing with vulnerable test access mechanisms. DAC 2008: 834-839

Shan Tang, Qiang Xu: In-band Cross-Trigger Event Transmission for Transaction-Based Debug. DATE 2008: 414-419

Feng Yuan, Lin Huang, Qiang Xu: Re-Examining the Use of Network-on-Chip as Test Access Mechanism. DATE 2008: 808-811

Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li: Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology. DATE 2008: 891-896

Jia Li, Qiang Xu, Yu Hu, Xiaowei Li: iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing. DATE 2008: 1184-1189

Jia Li, Qiang Xu, Yu Hu, Xiaowei Li: Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction. DELTA 2008: 26-31

Qiang Xu, Jaspal Subhlok: Construction and Evaluation of Coordinated Performance Skeletons. HiPC 2008: 73-86

Jia Li, Xiao Liu, Yubin Zhang, Yu Hu, Xiaowei Li, Qiang Xu: On capture power-aware test data compression for scan-based testing. ICCAD 2008: 67-72

Kai-xing Wu, Qiang Xu: Image Retrieval Based on Fuzzy Color Histogram. IIH-MSP 2008: 75-78

Jaspal Subhlok, Qiang Xu: Automatic construction of coordinated performance skeletons. IPDPS 2008: 1-5

Lin Huang, Qiang Xu: Is It Cost-Effective to Achieve Very High Fault Coverage for Testing Homogeneous SoCs with Core-Level Redundancy? ITC 2008: 1

Xiao Liu, Feng Yuan, Qiang Xu: A Generic Framework for Scan Capture Power Reduction in Test Compression Environment. ITC 2008: 1

Feng Yuan, Qiang Xu: SoC Test Architecture Design and Optimization Considering Power Supply Noise Effects. ITC 2008: 1-9

Lin Huang, Qiang Xu: On Modeling the Lifetime Reliability of Homogeneous Manycore Systems. PRDC 2008: 87-94

Qiang Xu, Baosheng Wang, André Ivanov, Fung Yu Young: Test scheduling for built-in self-tested embedded SRAMs with data retention faults. IET Computers & Digital Techniques 1(3): 256-264 (2007)

Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty: Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1539-1547 (2007)

Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty: SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects. DAC 2007: 676-681

Shan Tang, Qiang Xu: A multi-core debug platform for NoC-based systems. DATE 2007: 870-875

Qiang Xu, Dianwei Hu, Dong Xiang: Pattern-directed circuit virtual partitioning for test power reduction. ITC 2007: 1-10

Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty: Test-wrapper designs for the detection of signal-integrity faults on core-external interconnects of SoCs. ITC 2007: 1-9

Xiucheng Dong, Haibin Wang, Qiang Xu, Xiaoxiao Zhao: Research on Applications of a New-Type Fuzzy-Neural Network Controller. LSMS (1) 2007: 679-687

Qiang Xu, Nicola Nicolici: DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs. IEEE Trans. Computers 55(4): 470-485 (2006)

Qiang Xu, Nicola Nicolici: Multifrequency TAM design for hierarchical SOCs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 181-196 (2006)

Qiang Xu, Baosheng Wang, F. Y. Young: Retention-Aware Test Scheduling for BISTed Embedded SRAMs. European Test Symposium 2006: 83-88

Qiang Xu, Nicola Nicolici: Modular SOC testing with reduced wrapper count. IEEE Trans. on CAD of Integrated Circuits and Systems 24(12): 1894-1908 (2005)

Qiang Xu, Nicola Nicolici: Wrapper design for multifrequency IP cores. IEEE Trans. VLSI Syst. 13(6): 678-685 (2005)

Qiang Xu, Nicola Nicolici: Modular and rapid testing of SOCs with unwrapped logic blocks. IEEE Trans. VLSI Syst. 13(11): 1275-1285 (2005)

Ho Fai Ko, Qiang Xu, Nicola Nicolici: Register-transfer level functional scan for hierarchical designs. ASP-DAC 2005: 1172-1175

Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty: Multi-frequency wrapper design and optimization for embedded cores under average power constraints. DAC 2005: 123-128

Qiang Xu, Jaspal Subhlok: Automatic clustering of grid nodes. GRID 2005: 227-233

Qiang Xu, Nicola Nicolici: On concurrent test of wrapped cores and unwrapped logic blocks in SOCs. ITC 2005: 10

Qiang Xu, Nicola Nicolici: Multi-Frequency Test Access Mechanism Design for Modular SOC Testing. Asian Test Symposium 2004: 2-7

Qiang Xu, Nicola Nicolici: Wrapper Design for Testing IP Cores with Multiple Clock Domains. DATE 2004: 416-421

Qiang Xu: Content Management and Resources Integration: A Practice in Shanghai Digital Library. ICADL 2004: 25-34

Qiang Xu, Nicola Nicolici: Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores. ITC 2004: 1196-1202

Qiang Xu, Nicola Nicolici: Delay Fault Testing of Core-Based Systems-on-a-Chi. DATE 2003: 10744-10752

Bai Hong Fang, Qiang Xu, Nicola Nicolici: Hardware/Software Co-testing of Embedded Memories in Complex SOCs. ICCAD 2003: 599-606

Qiang Xu, Nicola Nicolici: On Reducing Wrapper Boundary Register Cells in Modular SOC Testing. ITC 2003: 622-631