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Hans-Joachim Wunderlich
2010 – today
- 2013
[c120]Marcus Wagner, Hans-Joachim Wunderlich: Efficient variation-aware statistical dynamic timing analysis for delay test applications. DATE 2013: 276-281- [c119]Stefan Hillebrecht, Michael A. Kochte, Dominik Erb, Hans-Joachim Wunderlich, Bernd Becker: Accurate QBF-based test pattern generation in presence of unknown values. DATE 2013: 436-441
- 2012
- [j32]Atefe Dalirsani, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich: Structural Test and Diagnosis for Graceful Degradation of NoC Switches. J. Electronic Testing 28(6): 831-841 (2012)
- [j31]Michael A. Kochte, Melanie Elm, Hans-Joachim Wunderlich: Accurate X-Propagation for Test Applications by SAT-Based Reasoning. IEEE Trans. on CAD of Integrated Circuits and Systems 31(12): 1908-1919 (2012)
- [c118]Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Hongyan Zhang, Hans-Joachim Wunderlich, Jörg Henkel: OTERA: Online test strategies for reliable reconfigurable architectures - Invited paper for the AHS-2012 special session "Dependability by reconfigurable hardware". AHS 2012: 38-45
- [c117]Stefan Holst, Eric Schneider, Hans-Joachim Wunderlich: Scan Test Power Simulation on GPGPUs. Asian Test Symposium 2012: 155-160
- [c116]Alejandro Cook, Dominik Ull, Melanie Elm, Hans-Joachim Wunderlich, Helmut Randoll, Stefan Dohren: Reuse of Structural Volume Test Methods for In-System Testing of Automotive ASICs. Asian Test Symposium 2012: 214-219
- [c115]Alexander Czutro, Michael E. Imhof, J. Jiang, Abdullah Mumtaz, Matthias Sauer, Bernd Becker, Ilia Polian, Hans-Joachim Wunderlich: Variation-Aware Fault Grading. Asian Test Symposium 2012: 344-349
- [c114]Claus Braun, Markus Daub, Alexander Scholl, Guido Schneider, Hans-Joachim Wunderlich: Parallel simulation of apoptotic receptor-clustering on GPGPU many-core architectures. BIBM 2012: 1-6
- [c113]Alejandro Cook, Sybille Hellebrand, Hans-Joachim Wunderlich: Built-in self-diagnosis exploiting strong diagnostic windows in mixed-mode test. European Test Symposium 2012: 1-6
- [c112]Nadereh Hatami, Rafal Baranowski, Paolo Prinetto, Hans-Joachim Wunderlich: Efficient system-level aging prediction. European Test Symposium 2012: 1-6
- [c111]Stefan Hillebrecht, Michael A. Kochte, Hans-Joachim Wunderlich, Bernd Becker: Exact stuck-at fault classification in presence of unknowns. European Test Symposium 2012: 1-6
- [c110]Claus Braun, Stefan Holst, Hans-Joachim Wunderlich, Juan Manuel Castillo-Sanchez, Joachim Gross: Acceleration of Monte-Carlo molecular simulations on hybrid computing architectures. ICCD 2012: 207-212
- [c109]Mohamed Abdelfattah, Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Hongyan Zhang, Jörg Henkel, Hans-Joachim Wunderlich: Transparent structural online test for reconfigurable systems. IOLTS 2012: 37-42
- [c108]Rafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich: Modeling, verification and pattern generation for reconfigurable scan networks. ITC 2012: 1-9
- [c107]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Michael E. Imhof, Hans-Joachim Wunderlich: A pseudo-dynamic comparator for error detection in fault tolerant architectures. VTS 2012: 50-55
- 2011
- [j30]Rafal Baranowski, Stefano Di Carlo, Nadereh Hatami, Michael E. Imhof, Michael A. Kochte, Paolo Prinetto, Hans-Joachim Wunderlich, Christian G. Zoellin: Efficient multi-level fault simulation of HW/SW systems for structural faults. SCIENCE CHINA Information Sciences 54(9): 1784-1796 (2011)
- [j29]Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich: Variation-aware fault modeling. SCIENCE CHINA Information Sciences 54(9): 1813-1826 (2011)
- [c106]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich: A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Asian Test Symposium 2011: 136-141
- [c105]Abdullah Mumtaz, Michael E. Imhof, Stefan Holst, Hans-Joachim Wunderlich: Embedded Test for Highly Accurate Defect Localization. Asian Test Symposium 2011: 213-218
- [c104]Alejandro Cook, Sybille Hellebrand, Thomas Indlekofer, Hans-Joachim Wunderlich: Diagnostic Test of Robust Circuits. Asian Test Symposium 2011: 285-290
- [c103]Michael A. Kochte, Sandip Kundu, Kohei Miyase, Xiaoqing Wen, Hans-Joachim Wunderlich: Efficient BDD-based Fault Simulation in Presence of Unknown Values. Asian Test Symposium 2011: 383-388
- [c102]Jörg Henkel, Lars Bauer, Joachim Becker, Oliver Bringmann, Uwe Brinkschulte, Samarjit Chakraborty, Michael Engel, Rolf Ernst, Hermann Härtig, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel Lohmann, Peter Marwedel, Marco Platzner, Wolfgang Rosenstiel, Ulf Schlichtmann, Olaf Spinczyk, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Hans-Joachim Wunderlich: Design and architectures for dependable embedded systems. CODES+ISSS 2011: 69-78
- [c101]Michael A. Kochte, Hans-Joachim Wunderlich: SAT-based fault coverage evaluation in the presence of unknown values. DATE 2011: 1303-1308
- [c100]Alejandro Cook, Melanie Elm, Hans-Joachim Wunderlich, Ulrich Abelein: Structural In-Field Diagnosis for Random Logic Circuits. European Test Symposium 2011: 111-116
- [c99]Atefe Dalirsani, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich: Structural Test for Graceful Degradation of NoC Switches. European Test Symposium 2011: 183-188
- [c98]Ilia Polian, Bernd Becker, Sybille Hellebrand, Hans-Joachim Wunderlich, Peter C. Maxwell: Towards Variation-Aware Test Methods. European Test Symposium 2011: 219-225
- [c97]Michael E. Imhof, Hans-Joachim Wunderlich: Soft error correction in embedded storage elements. IOLTS 2011: 169-174
- [c96]Rafal Baranowski, Hans-Joachim Wunderlich: Fail-safety in core-based system design. IOLTS 2011: 276-281
- [c95]Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich: SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures. ISLPED 2011: 33-38
- [c94]Abdullah Mumtaz, Michael E. Imhof, Hans-Joachim Wunderlich: P-PET: Partial pseudo-exhaustive test for high defect coverage. ITC 2011: 1-8
- 2010
- [j28]Michael A. Kochte, Christian G. Zoellin, Hans-Joachim Wunderlich: Efficient Concurrent Self-Test with Partially Specified Patterns. J. Electronic Testing 26(5): 581-594 (2010)
- [j27]Claus Braun, Hans-Joachim Wunderlich: Algorithmen-basierte Fehlertoleranz für Many-Core-Architekturen (Algorithm-based Fault-Tolerance on Many-Core Architectures). it - Information Technology 52(4): 209-215 (2010)
- [c93]Michael A. Kochte, Christian G. Zoellin, Rafal Baranowski, Michael E. Imhof, Hans-Joachim Wunderlich, Nadereh Hatami, Stefano Di Carlo, Paolo Prinetto: Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level. Asian Test Symposium 2010: 3-8
- [c92]Melanie Elm, Michael A. Kochte, Hans-Joachim Wunderlich: On Determining the Real Output Xs by SAT-Based Reasoning. Asian Test Symposium 2010: 39-44
- [c91]Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich: Variation-Aware Fault Modeling. Asian Test Symposium 2010: 87-93
- [c90]Michael A. Kochte, Marcel Schaal, Hans-Joachim Wunderlich, Christian G. Zoellin: Efficient fault simulation on many-core processors. DAC 2010: 380-385
- [c89]Melanie Elm, Hans-Joachim Wunderlich: BISD: Scan-based Built-In self-diagnosis. DATE 2010: 1243-1248
- [c88]Claus Braun, Hans-Joachim Wunderlich: Algorithm-based fault tolerance for many-core architectures. European Test Symposium 2010: 253
- [c87]Michael A. Kochte, Christian G. Zoellin, Rafal Baranowski, Michael E. Imhof, Hans-Joachim Wunderlich, Nadereh Hatami, Stefano Di Carlo, Paolo Prinetto: System reliability evaluation using concurrent multi-level simulation of structural faults. ITC 2010: 817
- [c86]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich: Parity prediction synthesis for nano-electronic gate designs. ITC 2010: 820
- [c85]Christian G. Zoellin, Hans-Joachim Wunderlich: Low-power test planning for arbitrary at-speed delay-test clock schemes. VTS 2010: 93-98
2000 – 2009
- 2009
- [j26]Stefan Holst, Hans-Joachim Wunderlich: Adaptive Debug and Diagnosis Without Fault Dictionaries. J. Electronic Testing 25(4-5): 259-268 (2009)
- [c84]Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Rauf Salimi Khaligh, Martin Radetzki, Hans-Joachim Wunderlich, Stefano Di Carlo, Paolo Prinetto: Test exploration and validation using transaction level models. DATE 2009: 1250-1253
- [c83]Stefan Holst, Hans-Joachim Wunderlich: A diagnosis algorithm for extreme space compaction. DATE 2009: 1355-1360
- [c82]Hans-Joachim Wunderlich: Software-Based Hardware Fault Tolerance for Many-Core Architectures. DFT 2009: 223-223
- [c81]Michael A. Kochte, Christian G. Zoellin, Hans-Joachim Wunderlich: Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead. European Test Symposium 2009: 53-58
- [c80]Michael A. Kochte, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich: Test Encoding for Extreme Response Compaction. European Test Symposium 2009: 155-160
- [c79]Abdul Wahid Hakmi, Stefan Holst, Hans-Joachim Wunderlich, Jürgen Schlöffel, Friedrich Hapke, Andreas Glowatz: Restrict Encoding for Mixed-Mode BIST. VTS 2009: 179-184
- 2008
- [c78]Melanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mäding: Scan chain clustering for test power reduction. DAC 2008: 828-833
- [c77]Melanie Elm, Hans-Joachim Wunderlich: Scan Chain Organization for Embedded Diagnosis. DATE 2008: 468-473
- [c76]Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Hans-Joachim Wunderlich: Test Set Stripping Limiting the Maximum Number of Specified Bits. DELTA 2008: 581-586
- [c75]Christian G. Zoellin, Hans-Joachim Wunderlich, Ilia Polian, Bernd Becker: Selective Hardening in Early Design Steps. European Test Symposium 2008: 185-190
- [c74]Stefan Holst, Hans-Joachim Wunderlich: Adaptive Debug and Diagnosis without Fault Dictionaries. European Test Symposium 2008: 199-204
- [c73]Michael E. Imhof, Hans-Joachim Wunderlich, Christian G. Zoellin: Integrating Scan Design and Soft Error Correction in Low-Power Applications. IOLTS 2008: 59-64
- [c72]Uranmandakh Amgalan, Christian Hachmann, Sybille Hellebrand, Hans-Joachim Wunderlich: Signature Rollback - A Technique for Testing Robust Circuits. VTS 2008: 125-130
- 2007
- [j25]Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers: Deterministic logic BIST for transition fault testing. IET Computers & Digital Techniques 1(3): 180-186 (2007)
- [c71]Michael E. Imhof, Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra: Scan Test Planning for Power Reduction. DAC 2007: 521-526
- [c70]Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich: Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. DDECS 2007: 185-190
- [c69]Sybille Hellebrand, Christian G. Zoellin, Hans-Joachim Wunderlich, Stefan Ludwig, Torsten Coym, Bernd Straube: A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. DFT 2007: 50-58
- [c68]Stefan Holst, Hans-Joachim Wunderlich: Adaptive Debug and Diagnosis without Fault Dictionaries. European Test Symposium 2007: 7-12
- [c67]Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich: An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. European Test Symposium 2007: 91-96
- [c66]Valentin Gherman, Hans-Joachim Wunderlich, R. D. Mascarenhas, Jürgen Schlöffel, Michael Garbers: Synthesis of irregular combinational functions with large don't care sets. ACM Great Lakes Symposium on VLSI 2007: 287-292
- [c65]Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Christian G. Zoellin, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Laurent Souef: Programmable deterministic Built-In Self-Test. ITC 2007: 1-9
- 2006
- [j24]Bernd Becker, Ilia Polian, Sybille Hellebrand, Bernd Straube, Hans-Joachim Wunderlich: DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems). it - Information Technology 48(5): 304- (2006)
- [j23]Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke: X-masking during logic BIST and its impact on defect coverage. IEEE Trans. VLSI Syst. 14(2): 193-202 (2006)
- [c64]
- [c63]Talal Arnaout, Gunter Bartsch, Hans-Joachim Wunderlich: Some Common Aspects of Design Validation, Debug and Diagnosis. DELTA 2006: 3-10
- [c62]Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers: Deterministic Logic BIST for Transition Fault Testing. European Test Symposium 2006: 123-130
- [c61]Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra: BIST Power Reduction Using Scan-Chain Disable in the Cell Processor. ITC 2006: 1-8
- [c60]Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich: Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. VLSI-SoC 2006: 403-408
- 2005
- [c59]Olivier Héron, Talal Arnaout, Hans-Joachim Wunderlich: On the Reliability Evaluation of SRAM-Based FPGA Designs. FPL 2005: 403-408
- [c58]Jun Zhou, Hans-Joachim Wunderlich: Software-basierender Selbsttest von Prozessorkernen unter Verlustleistungsbeschränkung. GI Jahrestagung (1) 2005: 441
- [c57]Pattara Kiatisevi, Luis Leonardo Azuara-Gomez, Rainer Dorsch, Hans-Joachim Wunderlich: Development of an audio player as system-on-a-chip using an open source platform. ISCAS (3) 2005: 2935-2938
- [c56]Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel: Implementing a Scheme for External Deterministic Self-Test. VTS 2005: 101-106
- 2004
- [j22]Hans-Joachim Wunderlich, Sandeep K. Shukla: Panel Summaries. IEEE Design & Test of Computers 21(1): 65-66 (2004)
- [c55]Talal Arnaout, Peter Göhner, Hans-Joachim Wunderlich, Eduard Zimmer: Reliability Considerations forMechatronic Systems on the Basis of a State Model. ARCS Workshops 2004: 106-112
- [c54]Harald P. E. Vranken, Ferry Syafei Sapei, Hans-Joachim Wunderlich: Impact of Test Point Insertion on Silicon Area and Timing during Layout. DATE 2004: 810-815
- [c53]Marie-Lise Flottes, Yves Bertrand, L. Balado, Emili Lupon, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, N. Pricopi, Hans-Joachim Wunderlich: Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ. DELTA 2004: 135-139
- [c52]Valentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers: Efficient Pattern Mapping for Deterministic Logic BIST. ITC 2004: 48-56
- [c51]Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker: X-Masking During Logic BIST and Its Impact on Defect Coverage. ITC 2004: 442-451
- 2003
- [j21]Shishpal Rawat, Hans-Joachim Wunderlich: Introduction. ACM Trans. Design Autom. Electr. Syst. 8(4): 397-398 (2003)
- [c50]Yves Bertrand, Marie-Lise Flottes, L. Balado, Joan Figueras, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, N. Pricopi, Hans-Joachim Wunderlich, J.-P. Van der Heyden: Test Engineering Education in Europe: the EuNICE-Test Project. MSE 2003: 85-86
- 2002
- [j20]Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich: High Defect Coverage with Low-Power Test Sequences in a BIST Environment. IEEE Design & Test of Computers 19(5): 44-52 (2002)
- [j19]Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich: Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. J. Electronic Testing 18(2): 159-170 (2002)
- [j18]Rainer Dorsch, Hans-Joachim Wunderlich: Reusing Scan Chains for Test Pattern Decompression. J. Electronic Testing 18(2): 231-240 (2002)
- [j17]Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich: A Mixed-Mode BIST Scheme Based on Folding Compression. J. Comput. Sci. Technol. 17(2): 203-212 (2002)
- [j16]Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik: Efficient Online and Offline Testing of Embedded DRAMs. IEEE Trans. Computers 51(7): 801-809 (2002)
- [c49]Rainer Dorsch, Ramón Huerta Rivera, Hans-Joachim Wunderlich, Martin Fischer: Adapting an SoC to ATE Concurrent Test Capabilities. ITC 2002: 1169-1175
- 2001
- [j15]Sybille Hellebrand, Huaguo Liang, Hans-Joachim Wunderlich: A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. J. Electronic Testing 17(3-4): 341-349 (2001)
- [j14]Gundolf Kiefer, Harald P. E. Vranken, Erik Jan Marinissen, Hans-Joachim Wunderlich: Application of Deterministic Logic BIST on Industrial Circuits. J. Electronic Testing 17(3-4): 351-362 (2001)
- [c48]A. Irion, Gundolf Kiefer, Harald P. E. Vranken, Hans-Joachim Wunderlich: Circuit partitioning for efficient logic BIST synthesis. DATE 2001: 86-91
- [c47]Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Hans-Joachim Wunderlich: On applying the set covering model to reseeding. DATE 2001: 156-161
- [c46]
- [c45]Michael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schünemann, Thomas Schwarz, Hans-Joachim Wunderlich: Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability. ITC 2001: 461-469
- [c44]
- [c43]Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich: Two-dimensional test data compression for scan-based deterministic BIST. ITC 2001: 894-902
- [c42]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich: A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. VTS 2001: 306-311
- 2000
- [j13]Gundolf Kiefer, Hans-Joachim Wunderlich: Deterministic BIST with Partial Scan. J. Electronic Testing 16(3): 169-177 (2000)
- [j12]Stefan Gerstendörfer, Hans-Joachim Wunderlich: Minimized Power Consumption for Scan-Based BIST. J. Electronic Testing 16(3): 203-212 (2000)
- [c41]Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich: Optimal Hardware Pattern Generation for Functional BIST. DATE 2000: 292-297
- [c40]Gundolf Kiefer, Hans-Joachim Wunderlich, Harald P. E. Vranken, Erik Jan Marinissen: Application of deterministic logic BIST on industrial circuits. ITC 2000: 105-114
- [c39]Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich: Non-intrusive BIST for systems-on-a-chip. ITC 2000: 644-651
- [c38]Sybille Hellebrand, Hans-Joachim Wunderlich, Huaguo Liang: A mixed mode BIST scheme based on reseeding of folding counters. ITC 2000: 778-784
1990 – 1999
- 1999
- [j11]Gundolf Kiefer, Hans-Joachim Wunderlich: Deterministic BIST with Multiple Scan Chains. J. Electronic Testing 14(1-2): 85-93 (1999)
- [c37]Sybille Hellebrand, Hans-Joachim Wunderlich, Vyacheslav N. Yarmolik: Symmetric Transparent BIST for RAMs. DATE 1999: 702-707
- [c36]Vyacheslav N. Yarmolik, I. V. Bykov, Sybille Hellebrand, Hans-Joachim Wunderlich: Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. EDCC 1999: 339-350
- [c35]Stefan Gerstendörfer, Hans-Joachim Wunderlich: Minimized power consumption for scan-based BIST. ITC 1999: 77-84
- [c34]Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik: Error Detecting Refreshment for Embedded DRAMs. VTS 1999: 384-390
- 1998
- [j10]Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig: Synthesizing Fast, Online-Testable Control Units. IEEE Design & Test of Computers 15(4): 36-41 (1998)
- [j9]Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig: Mixed-Mode BIST Using Embedded Processors. J. Electronic Testing 12(1-2): 127-138 (1998)
- [j8]
- [j7]Albrecht P. Stroele, Hans-Joachim Wunderlich: Hardware-optimal test register insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 17(6): 531-539 (1998)
- [c33]Madhavi Karkala, Nur A. Touba, Hans-Joachim Wunderlich: Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST. Asian Test Symposium 1998: 492-499
- [c32]Vyacheslav N. Yarmolik, Sybille Hellebrand, Hans-Joachim Wunderlich: Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. DATE 1998: 173-179
- [c31]
- [c30]Gundolf Kiefer, Hans-Joachim Wunderlich: Deterministic BIST with multiple scan chains. ITC 1998: 1057-1064
- [c29]Andre Hertwig, Sybille Hellebrand, Hans-Joachim Wunderlich: Fast Self-Recovering Controllers. VTS 1998: 296-302
- 1997
- [j6]Kwang-Ting Cheng, Kewal K. Saluja, Hans-Joachim Wunderlich: Guest Editorial. J. Electronic Testing 11(1): 7-8 (1997)
- [c28]Andre Hertwig, Hans-Joachim Wunderlich: Fast controllers for data dominated applications. ED&TC 1997: 84-89
- [c27]Gundolf Kiefer, Hans-Joachim Wunderlich: Using BIST Control for Pattern Generation. ITC 1997: 347-355
- [c26]Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian: Power Dissipation During Testing: Should We Worry About it? VTS 1997: 456-457
- 1996
- [c25]
- [c24]Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig: Mixed-Mode BIST Using Embedded Processors. ITC 1996: 195-204
- 1995
- [c23]Sybille Hellebrand, Birgit Reeb, Steffen Tarnick, Hans-Joachim Wunderlich: Pattern generation for a deterministic BIST scheme. ICCAD 1995: 88-94
- [c22]Albrecht P. Stroele, Hans-Joachim Wunderlich: Test register insertion with minimum hardware cost. ICCAD 1995: 95-101
- 1994
- [c21]Sybille Hellebrand, Hans-Joachim Wunderlich: Synthesis of Self-Testable Controllers. EDAC-ETC-EUROASIC 1994: 580-585
- [c20]Sybille Hellebrand, Hans-Joachim Wunderlich: An efficient procedure for the synthesis of fast self-testable controller structures. ICCAD 1994: 110-116
- [c19]Olaf Stern, Hans-Joachim Wunderlich: Simulation Results of an Efficient Defect-Analysis Procedure. ITC 1994: 729-738
- [c18]Albrecht P. Stroele, Hans-Joachim Wunderlich: Configuring Flip-Flops to BIST Registers. ITC 1994: 939-948
- 1992
- [j5]Hans-Joachim Wunderlich, Michael H. Schulz: Prüfgerechter Entwurf und Test hochintegrierter Schaltungen. Informatik Spektrum 15(1): 23-32 (1992)
- [j4]Hans-Joachim Wunderlich, Sybille Hellebrand: The pseudoexhaustive test of sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 11(1): 26-33 (1992)
- [j3]Bernhard Eschermann, Hans-Joachim Wunderlich: Optimized synthesis techniques for testable sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 11(3): 301-312 (1992)
- 1991
- [c17]Bernhard Eschermann, Hans-Joachim Wunderlich: A Unified Approach for the Synthesis of Self-Testable Finite State Machines. DAC 1991: 372-377
- [c16]Albrecht P. Stroele, Hans-Joachim Wunderlich: Signature Analysis and Test Scheduling for Self-Testable Circuits. FTCS 1991: 96-103
- [c15]Bernhard Eschermann, Hans-Joachim Wunderlich: Emulation of Scan Paths in Sequential Circuit Synthesis. Fault-Tolerant Computing Systems 1991: 136-147
- [c14]Thomas Kropf, Hans-Joachim Wunderlich: A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic. ITC 1991: 57-66
- 1990
- [j2]Arno Kunzmann, Hans-Joachim Wunderlich: An analytical approach to the partial scan problem. J. Electronic Testing 1(2): 163-174 (1990)
- [j1]Hans-Joachim Wunderlich: Multiple distributions for biased random test patterns. IEEE Trans. on CAD of Integrated Circuits and Systems 9(6): 584-593 (1990)
- [c13]Sybille Hellebrand, Hans-Joachim Wunderlich: Tools and devices supporting the pseudo-exhaustive test. EURO-DAC 1990: 13-17
- [c12]Peter C. Maxwell, Hans-Joachim Wunderlich: The effectiveness of different test sets for PLAs. EURO-DAC 1990: 628-632
- [c11]Bernhard Eschermann, Hans-Joachim Wunderlich: Optimized synthesis of self-testable finite state machines. FTCS 1990: 390-397
- [c10]Albrecht P. Stroele, Hans-Joachim Wunderlich: Error masking in self-testable circuits. ITC 1990: 544-552
- [c9]Sybille Hellebrand, Hans-Joachim Wunderlich, Oliver F. Haberl: Generating pseudo-exhaustive vectors for external testing. ITC 1990: 670-679
1980 – 1989
- 1989
- [c8]
- [c7]Sybille Hellebrand, Hans-Joachim Wunderlich: The Pseudo-Exhaustive Test of Sequential Circuits. ITC 1989: 19-27
- 1988
- [c6]Hans-Joachim Wunderlich, Sybille Hellebrand: Generating pattern sequences for the pseudo-exhaustive test of MOS-circuits. FTCS 1988: 36-41
- [c5]Sybille Hellebrand, Hans-Joachim Wunderlich: Automatisierung des Entwurfs vollständig testbarer Schaltungen. GI Jahrestagung (2) 1988: 145-159
- [c4]
- 1987
- [b1]Hans-Joachim Wunderlich: Probabilistische Verfahren für den Test hochintegrierter Schaltungen. Informatik-Fachberichte 140, Springer 1987, ISBN 3-540-18072-9
- [c3]Hans-Joachim Wunderlich: On Computing Optimized Input Probabilities for Random Tests. DAC 1987: 392-398
- 1986
- [c2]Hans-Joachim Wunderlich, Wolfgang Rosenstiel: On fault modeling for dynamic MOS circuits. DAC 1986: 540-546
- 1985
- [c1]
Coauthor Index
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last updated on 2013-05-26 01:48 CEST by the dblp team