Martin D. F. Wong

D. F. Wong

	2013
c227		Pei-Ci Wu, Qiang Ma, Martin D. F. Wong: An ILP-based automatic bus planner for dense PCBs. ASP-DAC 2013: 181-186
c226		Pei-Ci Wu, Martin D. F. Wong: Network flow modeling for escape routing on staggered pin arrays. ASP-DAC 2013: 193-198
c225		Yuelin Du, Hongbo Zhang, Qiang Ma, Martin D. F. Wong: Linear time algorithm to find all relocation positions for EUV defect mitigation. ASP-DAC 2013: 261-266
	2012
j96		Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng: A Practical Low-Power Nonregular Interconnect Design With Manufacturing for Design Approach. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 322-332 (2012)
j95		Tan Yan, Martin D. F. Wong: Correctly Model the Diagonal Capacity in Escape Routing. IEEE Trans. on CAD of Integrated Circuits and Systems 31(2): 285-293 (2012)
j94		Qiang Ma, Martin D. F. Wong: NP-Completeness and an Approximation Algorithm for Rectangle Escape Problem With Application to PCB Routing. IEEE Trans. on CAD of Integrated Circuits and Systems 31(9): 1356-1365 (2012)
c224		Lijuan Luo, Martin D. F. Wong, Lance Leong: Parallel implementation of R-trees on the GPU. ASP-DAC 2012: 353-358
c223		Yuelin Du, Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao: Hybrid lithography optimization with E-Beam and immersion processes for 16nm 1D gridded design. ASP-DAC 2012: 707-712
c222		Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Rasit O. Topalaglu: Efficient pattern relocation for EUV blank defect mitigation. ASP-DAC 2012: 719-724
c221		Qiang Ma, Hongbo Zhang, Martin D. F. Wong: Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology. DAC 2012: 591-596
c220		Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Yunfei Deng, Pawitter Mangat: Layout small-angle rotation and shift for EUV defect mitigation. ICCAD 2012: 43-49
c219		Haitong Tian, Hongbo Zhang, Qiang Ma, Zigang Xiao, Martin D. F. Wong: A polynomial time triple patterning algorithm for cell based row-structure layout. ICCAD 2012: 57-64
c218		Ting Yu, Zigang Xiao, Martin D. F. Wong: Efficient parallel power grid analysis via Additive Schwarz Method. ICCAD 2012: 399-406
c217		Ting Yu, Martin D. F. Wong: PGT_SOLVER: An efficient solver for power grid transient analysis. ICCAD 2012: 647-652
c216		Zigang Xiao, Yuelin Du, Hongbo Zhang, Martin D. F. Wong: A polynomial time exact algorithm for self-aligned double patterning layout decomposition. ISPD 2012: 17-24
c215		Martin D. F. Wong: On simulated annealing in EDA. ISPD 2012: 63-64
c214		Leslie Hwang, Kevin L. Lin, Martin D. F. Wong: Thermal via structural design in three-dimensional integrated circuits. ISQED 2012: 103-108
c213		Qiang Ma, Zigang Xiao, Martin D. F. Wong: Algorithmic study on the routing reliability problem. ISQED 2012: 483-488
	2011
j93		Lijuan Luo, Tan Yan, Qiang Ma, Martin D. F. Wong, Toshiyuki Shibuya: A New Strategy for Simultaneous Escape Based on Boundary Routing. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 205-214 (2011)
j92		Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang: Thermal-Driven Analog Placement Considering Device Matching. IEEE Trans. on CAD of Integrated Circuits and Systems 30(3): 325-336 (2011)
c212		Tan Yan, Qiang Ma, Scott Chilstedt, Martin D. F. Wong, Deming Chen: Routing with graphene nanoribbons. ASP-DAC 2011: 323-329
c211		Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao: Mask cost reduction with circuit performance consideration for self-aligned double patterning. ASP-DAC 2011: 787-792
c210		Qiang Ma, Hui Kong, Martin D. F. Wong, Evangeline F. Y. Young: A provably good approximation algorithm for Rectangle Escape Problem with application to PCB routing. ASP-DAC 2011: 843-848
c209		Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Rasit Onur Topaloglu: Self-aligned double patterning decomposition for overlay minimization and hot spot detection. DAC 2011: 71-76
c208		Qiang Ma, Evangeline F. Y. Young, Martin D. F. Wong: An optimal algorithm for layer assignment of bus escape routing on PCBs. DAC 2011: 176-181
c207		Hongbo Zhang, Tan Yan, Martin D. F. Wong, Sanjay J. Patel: Accelerating aerial image simulation with GPU. ICCAD 2011: 178-184
c206		Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao: Lithography-aware layout modification considering performance impact. ISQED 2011: 437-441
	2010
j91		Quang Dinh, Deming Chen, Martin D. F. Wong: A Routing Approach to Reduce Glitches in Low Power FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 235-240 (2010)
c205		Hui Kong, Tan Yan, Martin D. F. Wong: Optimal simultaneous pin assignment and escape routing for dense PCBs. ASP-DAC 2010: 275-280
c204		Qiang Ma, Martin D. F. Wong, Kai-Yuan Chao: Configurable multi-product floorplanning. ASP-DAC 2010: 549-554
c203		Quang Dinh, Deming Chen, Martin D. F. Wong: Dynamic power estimation for deep submicron circuits with process variation. ASP-DAC 2010: 587-592
c202		Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao: On process-aware 1-D standard cell design. ASP-DAC 2010: 838-842
c201		Lijuan Luo, Martin D. F. Wong, Wen-mei W. Hwu: An effective GPU implementation of breadth-first search. DAC 2010: 52-55
c200		Hui Kong, Qiang Ma, Tan Yan, Martin D. F. Wong: An optimal algorithm for finding disjoint rectangles and its application to PCB routing. DAC 2010: 212-217
c199		Tan Yan, Martin D. F. Wong: Recent research development in PCB layout. ICCAD 2010: 398-403
c198		Tan Yan, Pei-Ci Wu, Qiang Ma, Martin D. F. Wong: On the escape routing of differential pairs. ICCAD 2010: 614-620
c197		Quang Dinh, Deming Chen, Martin D. F. Wong: BDD-based circuit restructuring for reducing dynamic power. ICCD 2010: 548-554
c196		Lijuan Luo, Tan Yan, Qiang Ma, Martin D. F. Wong, Toshiyuki Shibuya: B-escape: a simultaneous escape routing algorithm based on boundary routing. ISPD 2010: 19-25
c195		Yu Zhong, Martin D. F. Wong: Fast block-iterative domain decomposition algorithm for IR drop analysis in large power grid. ISQED 2010: 277-283
c194		Qiang Ma, Tan Yan, Martin D. F. Wong: A negotiated congestion based router for simultaneous escape routing. ISQED 2010: 606-610
c193		Martin D. F. Wong: Advances in PCB routing. SLIP 2010: 33-34
	2009
j90		Huaizhi Wu, Martin D. F. Wong: Incremental Improvement of Voltage Assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 217-230 (2009)
j89		Muhammet Mustafa Ozdal, Martin D. F. Wong: Archer: A History-Based Global Routing Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 28(4): 528-540 (2009)
j88		Tan Yan, Martin D. F. Wong: BSG-Route: A Length-Constrained Routing Scheme for General Planar Topology. IEEE Trans. on CAD of Integrated Circuits and Systems 28(11): 1679-1690 (2009)
j87		Tan Yan, Martin D. F. Wong: Theories and algorithms on single-detour routing for untangling twisted bus. ACM Trans. Design Autom. Electr. Syst. 14(3) (2009)
c192		Lijuan Luo, Martin D. F. Wong: On using SAT to ordered escape problems. ASP-DAC 2009: 594-599
c191		Hui Kong, Tan Yan, Martin D. F. Wong: Automatic bus planner for dense PCBs. DAC 2009: 326-331
c190		Tan Yan, Martin D. F. Wong: A correct network flow model for escape routing. DAC 2009: 332-335
c189		Jia-Wei Fang, Martin D. F. Wong, Yao-Wen Chang: Flip-chip routing with unified area-I/O pad assignments for package-board co-design. DAC 2009: 336-339
c188		Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang: Thermal-driven analog placement considering device matching. DAC 2009: 593-598
c187		Tan Yan, Hui Kong, Martin D. F. Wong: Optimal layer assignment for escape routing of buses. ICCAD 2009: 245-248
c186		Quang Dinh, Deming Chen, Martin D. F. Wong: A routing approach to reduce glitches in low power FPGAs. ISPD 2009: 99-106
c185		Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng: Wire shaping is practical. ISPD 2009: 131-138
	2008
j86		Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger: Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 84-95 (2008)
j85		Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong: Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 621-632 (2008)
j84		Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong: Fast Dummy-Fill Density Analysis With Coupling Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 633-642 (2008)
j83		Lei Cheng, Deming Chen, Martin D. F. Wong: DDBDD: Delay-Driven BDD Synthesis for FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1203-1213 (2008)
j82		Lei Cheng, Deming Chen, Martin D. F. Wong: A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. ACM Trans. Design Autom. Electr. Syst. 13(2) (2008)
j81		Huaizhi Wu, Martin D. F. Wong, Wilsin Gosti: Postplacement voltage assignment under performance constraints. ACM Trans. Design Autom. Electr. Syst. 13(3) (2008)
j80		Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger: Optimal routing algorithms for rectilinear pin clusters in high-density multichip modules. ACM Trans. Design Autom. Electr. Syst. 13(4) (2008)
c184		Lijuan Luo, Martin D. F. Wong: Ordered escape routing based on Boolean satisfiability. ASP-DAC 2008: 244-249
c183		Quang Dinh, Deming Chen, Martin D. F. Wong: Efficient ASIP design for configurable processors with fine-grained resource sharing. FPGA 2008: 99-106
c182		Tan Yan, Martin D. F. Wong: BSG-Route: a length-matching router for general topology. ICCAD 2008: 499-505
c181		Yu Zhong, Martin D. F. Wong: Thermal-Aware IR Drop Analysis in Large Power Grid. ISQED 2008: 194-199
r1		Hannah Honghua Yang, Martin D. F. Wong: Circuit Partitioning: A Network-Flow-Based Balanced Min-Cut Approach. Encyclopedia of Algorithms 2008
	2007
j79		Huaizhi Wu, Martin D. F. Wong, I-Min Liu, Yusu Wang: Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1256-1269 (2007)
c180		David M. Pawlowski, Liang Deng, Martin D. F. Wong: Fast and Accurate OPC for Standard-Cell Layouts. ASP-DAC 2007: 7-12
c179		Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang: Coupling-aware Dummy Metal Insertion for Lithography. ASP-DAC 2007: 13-18
c178		Yu Zhong, Martin D. F. Wong: Fast Placement Optimization of Power Supply Pads. ASP-DAC 2007: 763-767
c177		Yu Zhong, Martin D. F. Wong: Efficient Second-Order Iterative Methods for IR Drop Analysis in Power Grid. ASP-DAC 2007: 768-773
c176		Lei Cheng, Deming Chen, Martin D. F. Wong: GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches. DAC 2007: 318-323
c175		Huaizhi Wu, Martin D. F. Wong: Improving Voltage Assignment by Outlier Detection and Incremental Placement. DAC 2007: 459-464
c174		Lei Cheng, Deming Chen, Martin D. F. Wong: DDBDD: Delay-Driven BDD Synthesis for FPGAs. DAC 2007: 910-915
c173		Lei Cheng, Deming Chen, Martin D. F. Wong, Mike Hutton, Jason Govig: Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains. ICCAD 2007: 370-375
c172		Hui Kong, Tan Yan, Martin D. F. Wong, Muhammet Mustafa Ozdal: Optimal bus sequencing for escape routing in dense PCBs. ICCAD 2007: 390-395
c171		Tan Yan, Martin D. F. Wong: Untangling twisted nets for bus routing. ICCAD 2007: 396-400
c170		Muhammet Mustafa Ozdal, Martin D. F. Wong: Archer: a history-driven global routing algorithm. ICCAD 2007: 488-495
c169		Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong: Dummy fill density analysis with coupling constraints. ISPD 2007: 3-10
c168		Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong: Is your layout density verification exact?: a fast exact algorithm for density calculation. ISPD 2007: 19-26
c167		Hua Xiang, Liang Deng, Li-Da Huang, Martin D. F. Wong: OPC-Friendly Bus Driven Floorplanning. ISQED 2007: 847-852
	2006
j78		Muhammet Mustafa Ozdal, Martin D. F. Wong: Algorithmic study of single-layer bus routing for high-speed boards. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 490-503 (2006)
j77		Muhammet Mustafa Ozdal, Martin D. F. Wong: Algorithms for simultaneous escape routing and Layer assignment of dense PCBs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1510-1522 (2006)
j76		Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong: Minimizing wire length in floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1744-1753 (2006)
j75		Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong: An ECO routing algorithm for eliminating coupling-capacitance violations. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1754-1762 (2006)
j74		Hung-Ming Chen, I-Min Liu, Martin D. F. Wong: I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2552-2556 (2006)
j73		Muhammet Mustafa Ozdal, Martin D. F. Wong: A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2784-2794 (2006)
j72		Lei Cheng, Martin D. F. Wong: Floorplan Design for Multimillion Gate FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2795-2805 (2006)
j71		Muhammet Mustafa Ozdal, Martin D. F. Wong: Two-layer bus routing for high-speed printed circuit boards. ACM Trans. Design Autom. Electr. Syst. 11(1): 213-227 (2006)
c166		Sebastian Vogel, Martin D. F. Wong: Closed form solution for optimal buffer sizing using the Weierstrass elliptic function. ASP-DAC 2006: 315-319
c165		Liang Deng, Martin D. F. Wong: An exact algorithm for the statistical shortest path problem. ASP-DAC 2006: 965-970
c164		Lei Cheng, Liang Deng, Deming Chen, Martin D. F. Wong: A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. DAC 2006: 117-120
c163		Huaizhi Wu, Martin D. F. Wong, I-Min Liu: Timing-constrained and voltage-island-aware voltage assignment. DAC 2006: 429-432
	2005
j70		Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong: Simultaneous power supply planning and noise avoidance in floorplan design. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 578-587 (2005)
j69		Hua Xiang, Xiaoping Tang, Martin D. F. Wong: An algorithm for integrated pin assignment and buffer planning. ACM Trans. Design Autom. Electr. Syst. 10(3): 561-572 (2005)
c162		Lei Cheng, Liang Deng, Martin D. F. Wong: Floorplanning for 3-D VLSI design. ASP-DAC 2005: 405-411
c161		Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong: Optimal redistribution of white space for wire length minimization. ASP-DAC 2005: 412-417
c160		Yongseok Cheon, Martin D. F. Wong: Crowdedness-balanced multilevel partitioning for uniform resource utilization. ASP-DAC 2005: 418-423
c159		Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wong: CMP aware shuttle mask floorplanning. ASP-DAC 2005: 1111-1114
c158		Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. Wong: Redundant-via enhanced maze routing for yield improvement. ASP-DAC 2005: 1148-1151
c157		Liang Deng, Martin D. F. Wong: Energy optimization in memory address bus structure for application-specific systems. ACM Great Lakes Symposium on VLSI 2005: 232-237
c156		Huaizhi Wu, I-Min Liu, Martin D. F. Wong, Yusu Wang: Post-placement voltage island generation under performance requirement. ICCAD 2005: 309-316
c155		Liang Deng, Martin D. F. Wong: Buffer insertion under process variations for delay minimization. ICCAD 2005: 317-321
c154		Yu Zhong, Martin D. F. Wong: Fast algorithms for IR drop analysis in large power grid. ICCAD 2005: 351-357
c153		Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger: An escape routing framework for dense boards with high-speed design constraints. ICCAD 2005: 759-766
c152		Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger: Optimal routing algorithms for pin clusters in high-density multichip modules. ICCAD 2005: 767-774
c151		Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong: Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer. ISQED 2005: 181-186
c150		Muzhou Shao, Youxin Gao, Li-Pen Yuan, Hung-Ming Chen, Martin D. F. Wong: Current Calculation on VLSI Signal Interconnects. ISQED 2005: 580-585
c149		Hua Xiang, I-Min Liu, Martin D. F. Wong: Wire Planning with Bounded Over-the-Block Wires. ISQED 2005: 622-627
c148		Muzhou Shao, Youxin Gao, Li-Pen Yuan, Martin D. F. Wong: IR Drop and Ground Bounce Awareness Timing Model. ISVLSI 2005: 226-231
	2004
j68		Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, I-Min Liu: A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 141-147 (2004)
j67		Hua Xiang, Xiaoping Tang, Martin D. F. Wong: Bus-driven floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 23(11): 1522-1530 (2004)
c147		Xiaoping Tang, Martin D. F. Wong: On handling arbitrary rectilinear shape constraint. ASP-DAC 2004: 38-41
c146		Xiaoping Tang, Martin D. F. Wong: Tradeoff routing resource, runtime and quality in buffered routing. ASP-DAC 2004: 430-433
c145		Li-Da Huang, Martin D. F. Wong: Optical proximity correction (OPC): friendly maze routing. DAC 2004: 186-191
c144		Liang Deng, Martin D. F. Wong: Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus. DATE 2004: 1104-1109
c143		Lei Cheng, Martin D. F. Wong: Floorplan design for multi-million gate FPGAs. ICCAD 2004: 292-299
c142		Muhammet Mustafa Ozdal, Martin D. F. Wong: Simultaneous escape routing and layer assignment for dense PCBs. ICCAD 2004: 822-829
c141		Muhammet Mustafa Ozdal, Martin D. F. Wong: A provably good algorithm for high performance bus routing. ICCAD 2004: 830-837
c140		Muhammet Mustafa Ozdal, Martin D. F. Wong: A Two-Layer Bus Routing Algorithm for High-Speed Boards. ICCD 2004: 99-105
c139		Martin D. F. Wong: Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers. ICCD 2004: 106-110
c138		Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang: I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. ICCD 2004: 562-567
c137		Esra Erdem, Martin D. F. Wong: Rectilinear Steiner Tree Construction Using Answer Set Programming. ICLP 2004: 386-399
c136		Hua Xiang, Kai-Yuan Chao, D. F. Wong: An ECO algorithm for eliminating crosstalk violations. ISPD 2004: 41-46
	2003
j66		Li-Da Huang, Minghorng Lai, Martin D. F. Wong, Youxin Gao: Maze routing with buffer insertion under transition time constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 91-95 (2003)
j65		Yongseok Cheon, Martin D. F. Wong: Design hierarchy-guided multilevel circuit partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 420-427 (2003)
j64		Seokjin Lee, Martin D. F. Wong: Timing-driven routing for FPGAs based on Lagrangian relaxation. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 506-510 (2003)
j63		Hua Xiang, Xiaoping Tang, Martin D. F. Wong: Min-cost flow-based algorithm for simultaneous pin assignment and routing. IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 870-878 (2003)
j62		Yao-Wen Chang, Kai Zhu, Guang-Ming Wu, D. F. Wong, C. K. Wong: Analysis of FPGA/FPIC switch modules. ACM Trans. Design Autom. Electr. Syst. 8(1): 11-37 (2003)
c135		Muzhou Shao, D. F. Wong, Youxin Gao, Huijing Cao, Li-Pen Yuan: A fast and accurate method for interconnect current calculation. ASP-DAC 2003: 37-42
c134		Hung-Ming Chen, Li-Da Huang, I-Min Liu, Minghorng Lai, D. F. Wong: Floorplanning with power supply noise avoidance. ASP-DAC 2003: 427-430
c133		John F. Croix, D. F. Wong: Blade and razor: cell and interconnect delay analysis using current-based models. DAC 2003: 386-389
c132		Li-Da Huang, Hung-Ming Chen, D. F. Wong: Global Wire Bus Configuration with Minimum Delay Uncertainty. DATE 2003: 10050-10055
c131		Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun: Wire type assignment for FPGA routing. FPGA 2003: 61-67
c130		Hua Xiang, Xiaoping Tang, Martin D. F. Wong: Bus-Driven Floorplanning. ICCAD 2003: 66-73
c129		Seokjin Lee, Yongseok Cheon, Martin D. F. Wong: A Min-Cost Flow Based Detailed Router for FPGAs. ICCAD 2003: 388-393
c128		Muhammet Mustafa Ozdal, Martin D. F. Wong: Length-Matching Routing for High-Speed Printed Circuit Boards. ICCAD 2003: 394-400
c127		Yongseok Cheon, Seokjin Lee, Martin D. F. Wong: Stable Multiway Circuit Partitioning for ECO. ICCAD 2003: 718-725
c126		Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxin Gao, Li-Pen Yuan, Li-Da Huang, Seokjin Lee: Explicit gate delay model for timing evaluation. ISPD 2003: 32-38
	2002
j61		Ruiqi Tian, Xiaoping Tang, Martin D. F. Wong: Dummy-feature placement for chemical-mechanical polishinguniformity in a shallow-trench isolation process. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 63-71 (2002)
j60		Minghorng Lai, Martin D. F. Wong: Maze routing with buffer insertion and wiresizing. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1205-1209 (2002)
c125		Hua Xiang, D. F. Wong, Xiaoping Tang: An algorithm for integrated pin assignment and buffer planning. DAC 2002: 584-589
c124		Xiaoping Tang, D. F. Wong: Floorplanning with alignment and performance constraints. DAC 2002: 848-853
c123		Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu: A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. DATE 2002: 470-475
c122		Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao: Maze Routing with Buffer Insertion under Transition Time Constraints. DATE 2002: 702-707
c121		K. K. Lee, D. F. Wong: Incremental reconfiguration of multi-FPGA systems. FPGA 2002: 206-213
c120		Hua Xiang, Kai-Yuan Chao, D. F. Wong: ECO algorithms for removing overlaps between power rails and signal wires. ICCAD 2002: 67-74
c119		Muzhou Shao, D. F. Wong, Youxin Gao, Li-Pen Yuan, Huijing Cao: Shaping interconnect for uniform current density. ICCAD 2002: 254-259
c118		Ruiqi Tian, Ronggang Yu, Xiaoping Tang, D. F. Wong: On mask layout partitioning for electron projection lithography. ICCAD 2002: 514-518
c117		Yongseok Cheon, D. F. Wong: Design hierarchy guided multilevel circuit partitioning. ISPD 2002: 30-35
c116		Seokjin Lee, D. F. Wong: Timing-driven routing for FPGAs based on Lagrangian relaxation. ISPD 2002: 176-181
	2001
j59		Chris C. N. Chu, D. F. Wong: VLSI Circuit Performance Optimization by Geometric Programming. Annals OR 105(1-4): 37-60 (2001)
j58		Xiaoping Tang, D. F. Wong: Network flow based buffer planning. Integration 30(2): 143-155 (2001)
j57		Yao-Wen Chang, Jai-Ming Lin, Martin D. F. Wong: Matching-based algorithm for FPGA channel segmentation design. IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 784-791 (2001)
j56		Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang: On extending slicing floorplan to handle L/T-shaped modules andabutment constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 800-807 (2001)
j55		Ruiqi Tian, Martin D. F. Wong, Robert Boone: Model-based dummy feature placement for oxide chemical-mechanicalpolishing manufacturability. IEEE Trans. on CAD of Integrated Circuits and Systems 20(7): 902-910 (2001)
j54		Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong: Fast evaluation of sequence pair in block placement by longestcommon subsequence computation. IEEE Trans. on CAD of Integrated Circuits and Systems 20(12): 1406-1413 (2001)
j53		Chris C. N. Chu, D. F. Wong: Closed form solutions to simultaneous buffer insertion/sizing and wire sizing. ACM Trans. Design Autom. Electr. Syst. 6(3): 343-371 (2001)
c115		Minghorng Lai, D. F. Wong: Memory-efficient interconnect optimization. ASP-DAC 2001: 198-202
c114		Xiaoping Tang, D. F. Wong: FAST-SP: a fast algorithm for block placement based on sequence pair. ASP-DAC 2001: 521-526
c113		Youxin Gao, D. F. Wong: A fast and accurate delay estimation method for buffered interconnects. ASP-DAC 2001: 533-538
c112		I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong: Integrated power supply planning and floorplanning. ASP-DAC 2001: 589-594
c111		Minghorng Lai, D. F. Wong: Slicing tree is a complete floorplan representation. DATE 2001: 228-232
c110		Youxin Gao, D. F. Wong: A graph based algorithm for optimal buffer insertion under accurate delay models. DATE 2001: 535-539
c109		K. K. Lee, D. F. Wong: LRoute: a delay minimal router for hierarchical CPLDs. FPGA 2001: 12-20
c108		Hung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang: Faster and more accurate wiring evaluation in interconnect-centric floorplanning. ACM Great Lakes Symposium on VLSI 2001: 62-67
c107		Xiaoping Tang, Ruiqi Tian, Hua Xiang, D. F. Wong: A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints. ICCAD 2001: 49-56
c106		Hua Xiang, Xiaoping Tang, D. F. Wong: An Algorithm for Simultaneous Pin Assignment and Routing. ICCAD 2001: 232-
c105		Ruiqi Tian, Xiaoping Tang, D. F. Wong: Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process. ISPD 2001: 118-123
	2000
j52		Wai-Kei Mak, D. F. Wong: A fast hypergraph min-cut algorithm for circuit partitioning. Integration 30(1): 1-11 (2000)
j51		Martin D. F. Wong, Dwight D. Hill: Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 173-174 (2000)
j50		Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang: Slicing floorplans with range constraint. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 272-278 (2000)
j49		Hai Zhou, Martin D. F. Wong, I-Min Liu, Adnan Aziz: Simultaneous routing and buffer insertion with restrictions onbuffer locations. IEEE Trans. on CAD of Integrated Circuits and Systems 19(7): 819-824 (2000)
j48		Yao-Wen Chang, Kai Zhu, D. F. Wong: Timing-driven routing for symmetrical array-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 5(3): 433-450 (2000)
c104		Esra Erdem, Vladimir Lifschitz, Martin D. F. Wong: Wire Routing and Satisfiability Planning. Computational Logic 2000: 822-836
c103		Hai Zhou, D. F. Wong: Optimal low power X OR gate decomposition. DAC 2000: 104-107
c102		Minghorng Lai, D. F. Wong: Maze routing with buffer insertion and wiresizing. DAC 2000: 374-378
c101		Ruiqi Tian, D. F. Wong, Robert Boone: Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability. DAC 2000: 667-670
c100		Xiaoping Tang, D. F. Wong, Ruiqi Tian: Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation. DATE 2000: 106-111
c99		I-Min Liu, Adnan Aziz, D. F. Wong: Meeting Delay Constraints in DSM by Minimal Repeater Insertion. DATE 2000: 436-440
c98		Youxin Gao, D. F. Wong: Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model. DATE 2000: 512-516
c97		I-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong: Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. ISPD 2000: 33-38
c96		Xiaoping Tang, D. F. Wong: Planning buffer locations by network flows. ISPD 2000: 180-185
	1999
j47		Youxin Gao, D. F. Wong: Shaping a VLSI wire to minimize Elmore delay with consideration of coupling capacitance. Integration 27(2): 165-178 (1999)
j46		Fung Yu Young, Chris C. N. Chu, D. F. Wong: Generation of Universal Series-Parallel Boolean Functions. J. ACM 46(3): 416-435 (1999)
j45		Chris C. N. Chu, Martin D. F. Wong: Greedy wire-sizing is linear time. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 398-405 (1999)
j44		Chris C. N. Chu, Martin D. F. Wong: A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 787-798 (1999)
j43		Youxin Gao, Martin D. F. Wong: Optimal shape function for a bidirectional wire under Elmore delay model. IEEE Trans. on CAD of Integrated Circuits and Systems 18(7): 994-999 (1999)
j42		Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong: Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. IEEE Trans. on CAD of Integrated Circuits and Systems 18(7): 1014-1025 (1999)
j41		Chris C. N. Chu, Martin D. F. Wong: An efficient and optimal algorithm for simultaneous buffer and wire sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1297-1304 (1999)
j40		Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang: Slicing floorplans with boundary constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1385-1389 (1999)
j39		Hai Zhou, Martin D. F. Wong: Global routing with crosstalk constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1683-1688 (1999)
j38		Youxin Gao, Martin D. F. Wong: Wire-sizing optimization with inductance consideration using transmission-line model. IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1759-1767 (1999)
c95		Fung Yu Young, D. F. Wong: Slicing Floorplans with Boundary Constraint. ASP-DAC 1999: 17-20
c94		Youxin Gao, D. F. Wong: Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model. ASP-DAC 1999: 217-220
c93		Chung-Ping Chen, D. F. Wong: Error Bounded Padé Approximation via Bilinear Conformal Transformation. DAC 1999: 7-12
c92		Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz: Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. DAC 1999: 96-99
c91		Huiqun Liu, D. F. Wong: Circuit Partitioning for Dynamically Reconfigurable FPGAs. FPGA 1999: 187-194
c90		Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani: Integrated floorplanning and interconnect planning. ICCAD 1999: 354-357
c89		Huiqun Liu, D. F. Wong: A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning. ICCAD 1999: 400-405
c88		Jacob White, Jacob Avidan, Abe Elfadel, D. F. Wong: Advances in transistor timing, simulation, and optimization (tutorial abstract). ICCAD 1999: 611
c87		I-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou: An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. ICCD 1999: 210-215
c86		K. K. Lee, D. F. Wong: An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAs. ICCD 1999: 216-221
c85		Wai-Kei Mak, D. F. Wong: A fast hypergraph minimum cut algorithm. ISCAS (6) 1999: 170-173
c84		Fung Yu Young, D. F. Wong: Slicing floorplans with range constraint. ISPD 1999: 97-102
	1998
j37		Huiqun Liu, Martin D. F. Wong: Network-flow-based multiway partitioning with area and pin constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 50-59 (1998)
j36		Kai Zhu, Martin D. F. Wong: Switch bound allocation for maximizing routability in timing-driven routing of FPGA's. IEEE Trans. on CAD of Integrated Circuits and Systems 17(4): 316-323 (1998)
j35		Chris C. N. Chu, Martin D. F. Wong: A matrix synthesis approach to thermal placement. IEEE Trans. on CAD of Integrated Circuits and Systems 17(11): 1166-1174 (1998)
j34		Hannah Honghua Yang, Martin D. F. Wong: Optimal min-area min-cut replication in partitioned circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 17(11): 1175-1183 (1998)
j33		Hai Zhou, D. F. Wong: Optimal river routing with crosstalk constraints. ACM Trans. Design Autom. Electr. Syst. 3(3): 496-514 (1998)
c83		Hai Zhou, D. F. Wong: Global Routing with Crosstalk Constraints. DAC 1998: 374-377
c82		Madhukar R. Korupolu, K. K. Lee, D. F. Wong: Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs. DAC 1998: 708-711
c81		Chris C. N. Chu, D. F. Wong: A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing. DATE 1998: 479-485
c80		Huiqun Liu, Kai Zhu, D. F. Wong: Circuit Partitioning with Complex Resource Constraints in FPGAs. FPGA 1998: 77-84
c79		Wai-Kei Mak, D. F. Wong: Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract). FPGA 1998: 260
c78		Yao-Wen Chang, Jai-Ming Lin, D. F. Wong: Graph matching-based algorithms for FPGA segmentation design. ICCAD 1998: 34-39
c77		Fung Yu Young, D. F. Wong: Slicing floorplans with pre-placed modules. ICCAD 1998: 252-258
c76		Huiqun Liu, D. F. Wong: Network flow based circuit partitioning for time-multiplexed FPGAs. ICCAD 1998: 497-504
c75		Youxin Gao, D. F. Wong: Shaping a VLSI wire to minimize delay using transmission line model. ICCAD 1998: 611-616
c74		Chung-Ping Chen, Chris C. N. Chu, D. F. Wong: Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. ICCAD 1998: 617-624
c73		Wai-Kei Mak, D. F. Wong: Performance-driven board-level routing for FPGA-based logic emulation. ICCD 1998: 199-201
c72		Huiqun Liu, D. F. Wong: Integrated partitioning and scheduling for hardware/software co-design. ICCD 1998: 609-614
c71		Kai Zhu, Yao-Wen Chang, D. F. Wong: Timing-driven routing for symmetrical-array-based FPGAs. ICCD 1998: 628-633
c70		Chris C. N. Chu, D. F. Wong: Greedy wire-sizing is linear time. ISPD 1998: 39-44
	1997
j32		F. Y. Young, D. F. Wong: How good are slicing floorplans? Integration 23(1): 61-73 (1997)
j31		Y. P. Chen, D. F. Wong: On retiming for FPGA logic module minimization. Integration 24(2): 135-145 (1997)
j30		Y. P. Chen, D. F. Wong: A graph theoretic approach to feed-through pin assignment. Integration 24(2): 147-158 (1997)
j29		Shashidhar Thakur, Yao-Wen Chang, Martin D. F. Wong, S. Muthukrishnan: Algorithms for an FPGA switch module routing problem with application to global routing. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 32-46 (1997)
j28		Wai-Kei Mak, Martin D. F. Wong: On optimal board-level routing for FPGA-based logic emulation. IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 282-289 (1997)
j27		Kai Zhu, Martin D. F. Wong: Clock skew minimization during FPGA placement. IEEE Trans. on CAD of Integrated Circuits and Systems 16(4): 376-385 (1997)
j26		T. W. Her, Martin D. F. Wong: Module implementation selection and its application to transistor placement. IEEE Trans. on CAD of Integrated Circuits and Systems 16(6): 645-651 (1997)
j25		Hannah Honghua Yang, Martin D. F. Wong: Circuit clustering for delay minimization under area and pin constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 976-986 (1997)
j24		Wai-Kei Mak, Martin D. F. Wong: Minimum replication min-cut partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1221-1227 (1997)
j23		Wai-Kei Mak, D. F. Wong: Board-level multiterminal net routing for FPGA-based logic emulation. ACM Trans. Design Autom. Electr. Syst. 2(2): 151-167 (1997)
c69		John F. Croix, D. F. Wong: A Fast And Accurate Technique To Optimize Characterization Tables For Logic Synthesis. DAC 1997: 337-340
c68		Chung-Ping Chen, D. F. Wong: Optimal Wire-Sizing Function with Fringing Capacitance Consideration. DAC 1997: 604-607
c67		Hai Zhou, D. F. Wong: An exact gate decomposition algorithm for low-power technology mapping. ICCAD 1997: 575-580
c66		Chris C. N. Chu, D. F. Wong: A new approach to simultaneous buffer insertion and wire sizing. ICCAD 1997: 614-621
c65		Youxin Gao, D. F. Wong: Optimal shape function for a bi-directional wire under Elmore delay model. ICCAD 1997: 622-627
c64		Ashih D. Mehta, Yao-Ping Chen, Noel Menezes, D. F. Wong, Lawrence T. Pileggi: Clustering and Load Balancing for Buffered Clock Tree Synthesis. ICCD 1997: 217-223
c63		Fung Yu Young, D. F. Wong: On the Construction of Universal Series-Parallel Functions for Logic Module Design. ICCD 1997: 482-488
c62		Wai-Kei Mak, D. F. Wong: Channel Segmentation Design for Symmentrical FPGAs. ICCD 1997: 496-501
c61		Hai Zhou, D. F. Wong: Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation. ICCD 1997: 628-633
c60		Huiqun Liu, D. F. Wong: Network flow based multi-way partitioning with area and pin constraints. ISPD 1997: 12-17
c59		Fung Yu Young, D. F. Wong: How good are slicing floorplans?. ISPD 1997: 144-149
c58		Chris C. N. Chu, D. F. Wong: A matrix synthesis approach to thermal placement. ISPD 1997: 163-168
c57		Chris C. N. Chu, D. F. Wong: Closed form solution to simultaneous buffer insertion/sizing and wire sizing. ISPD 1997: 192-197
	1996
j22		Shashidhar Thakur, D. F. Wong: Simultaneous area and delay minimum K-LUT mapping for K-exact networks. Integration 20(3): 287-302 (1996)
j21		Glenn G. Lai, Donald S. Fussell, Martin D. F. Wong: Hinted quad trees for VLSI geometry DRC based on efficient searching for neighbors. IEEE Trans. on CAD of Integrated Circuits and Systems 15(3): 317-324 (1996)
j20		Mohankumar Guruswamy, Martin D. F. Wong: Echelon: a multilayer detailed area router. IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1126-1136 (1996)
j19		Hannah Honghua Yang, Martin D. F. Wong: Balanced partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1533-1540 (1996)
j18		Yao-Wen Chang, D. F. Wong, C. K. Wong: Universal switch modules for FPGA design. ACM Trans. Design Autom. Electr. Syst. 1(1): 80-101 (1996)
j17		Shashidhar Thakur, D. F. Wong: Series-parallel functions and FPGA logic module design. ACM Trans. Design Autom. Electr. Syst. 1(1): 102-122 (1996)
c56		Shashidhar Thakur, D. F. Wong, Shankar Krishnamoorthy: Delay Minimal Decomposition of Multiplexers in Technology Mapping. DAC 1996: 254-257
c55		Chung-Ping Chen, Yao-Wen Chang, D. F. Wong: Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. DAC 1996: 405-408
c54		Chung-Ping Chen, Yao-Ping Chen, D. F. Wong: Optimal Wire-Sizing Formular Under the Elmore Delay Model. DAC 1996: 487-490
c53		Shashidhar Thakur, D. F. Wong: Universal Logic Modules for Series-Parallel Functions. FPGA 1996: 31-37
c52		Yao-Wen Chang, D. F. Wong, C. K. Wong: Universal Switch-Module Design for Symmetric-Array-Based FPGAs. FPGA 1996: 80-86
c51		Chung-Ping Chen, Hai Zhou, D. F. Wong: Optimal non-uniform wire-sizing under the Elmore delay model. ICCAD 1996: 38-43
c50		Wai-Kei Mak, D. F. Wong: Minimum replication min-cut partitioning. ICCAD 1996: 205-210
c49		Hai Zhou, D. F. Wong: An optimal algorithm for river routing with crosstalk constraints. ICCAD 1996: 310-315
c48		Yung-Ming Fang, D. F. Wong: Multiplexor Network Generation in High Level Synthesis. ICCD 1996: 78-
	1995
j16		Ting-Chi Wang, Martin D. F. Wong, Yachyang Sun, Chak-Kuen Wong: Optimal net assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 14(2): 265-269 (1995)
j15		T. W. Her, Martin D. F. Wong: On over-the-cell channel routing with cell orientations consideration. IEEE Trans. on CAD of Integrated Circuits and Systems 14(6): 766-772 (1995)
j14		T. W. Her, Ting-Chi Wang, Martin D. F. Wong: Performance-driven channel pin assignment algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 14(7): 849-857 (1995)
j13		Rajmohan Rajaraman, Martin D. F. Wong: Optimum clustering for delay minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1490-1495 (1995)
c47		Wai-Kei Mak, D. F. Wong: On Optimal Board-Level Routing for FPGA-Based Logic Emulation. DAC 1995: 552-556
c46		Shashidhar Thakur, D. F. Wong: On Designing ULM-based FPGA Logic Modules. FPGA 1995: 3-9
c45		Hannah Honghua Yang, D. F. Wong: New algorithms for min-cut replication in partitioned circuits. ICCAD 1995: 216-222
c44		Wai-Kei Mak, D. F. Wong: Board-level multi-terminal net routing for FPGA-based logic emulation. ICCAD 1995: 339-344
c43		Kai-Yuan Chao, D. F. Wong: Signal integrity optimization on the pad assignment for high-speed VLSI design. ICCAD 1995: 720-725
c42		Kai-Yuan Chao, D. F. Wong: Thermal placement for high-performance multichip modules. ICCD 1995: 218-223
c41		Yao-Wen Chang, D. F. Wong, C. K. Wong: FPGA global routing based on a new congestion metric. ICCD 1995: 372-
c40		Yao-Wen Chang, D. F. Wong, C. K. Wong: Design and analysis of FPGA/FPIC switch modules. ICCD 1995: 394-401
c39		Shashidhar Thakur, D. F. Wong: Simultaneous area and delay minimum K-LUT mapping for K-exact networks. ICCD 1995: 402-408
c38		Kai-Yuan Chao, D. F. Wong: Floorplanning for Low Power Designs. ISCAS 1995: 45-48
c37		Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong: An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing. ISCAS 1995: 207-210
c36		Yao-Ping Chen, D. F. Wong: A Graph Theoretic Approach to Feed-Through Pin Assignment. ISCAS 1995: 1687-1690
	1994
j12		Yang Cai, Martin D. F. Wong: On shifting blocks and terminals to minimize channel density. IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 178-186 (1994)
c35		Kai Zhu, D. F. Wong: Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs. DAC 1994: 165-170
c34		Kai Zhu, D. F. Wong: Clock Skew Minimization During FPGA Placement. DAC 1994: 232-237
c33		Shashidhar Thakur, D. F. Wong, S. Muthukrishnan: Algorithms for a switch module routing problem. EURO-DAC 1994: 265-270
c32		Honghua Yang, D. F. Wong: Efficient network flow based min-cut balanced partitioning. ICCAD 1994: 50-55
c31		Hannah Honghua Yang, D. F. Wong: Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs. ICCAD 1994: 150-155
c30		Yung-Ming Fang, D. F. Wong: Simultaneous functional-unit binding and floorplanning. ICCAD 1994: 317-321
c29		Yao-Wen Chang, Shashidhar Thakur, Kai Zhu, D. F. Wong: A new global routing algorithm for FPGAs. ICCAD 1994: 356-361
c28		Kai-Yuan Chao, D. F. Wong: Layer assignment for high-performance multi-chip modules. ICCAD 1994: 680-685
c27		Yao-Ping Chen, D. F. Wong: On Retiming for FPGA Logic Module Minimization. ICCD 1994: 394-397
c26		T. W. Her, D. F. Wong: Over-the-Cell Routing with Cell Orientations Consideration. ISCAS 1994: 471-474
	1993
j11		Yang Cai, Martin D. F. Wong: On minimizing the number of L-shaped channels in building-block layout [VLSI]. IEEE Trans. on CAD of Integrated Circuits and Systems 12(6): 757-769 (1993)
j10		Yang Cai, Martin D. F. Wong: Efficient via shifting algorithms in channel compaction. IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1848-1857 (1993)
c25		Glenn G. Lai, Donald S. Fussell, D. F. Wong: HV/VH Trees: A New Spatial Data Structure for Fast Region Queries. DAC 1993: 43-47
c24		Rajmohan Rajaraman, D. F. Wong: Optimal Clustering for Delay Minimization. DAC 1993: 309-314
c23		Kai Zhu, D. F. Wong, Yao-Wen Chang: Switch module design with application to two-dimensional segmentation design. ICCAD 1993: 480-485
c22		Yao-Ping Chen, Ting-Chi Wang, D. F. Wong: A Graph Partitioning Problem for Multiple-chip Design. ISCAS 1993: 1778-1781
c21		Yao-Ping Chen, D. F. Wong: On optimal approximation of orthogonal polygons. ISCAS 1993: 2533-2536
	1992
j9		Ting-Chi Wang, Martin D. F. Wong: Optimal floorplan area optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 11(8): 992-1002 (1992)
j8		Shinichiro Haruyama, Martin D. F. Wong, Donald S. Fussell: Topological channel routing [VLSI]. IEEE Trans. on CAD of Integrated Circuits and Systems 11(10): 1177-1197 (1992)
c20		Ting-Chi Wang, D. F. Wong: A Graph Theoretic Technique to Speed up Floorplan Area Optimization. DAC 1992: 62-68
c19		Kai Zhu, D. F. Wong: On channel segmentation design for row-based FPGAs. ICCAD 1992: 26-29
c18		Yang Cai, D. F. Wong: Channel Density Minimization by Pin Permutation. ICCD 1992: 378-382
	1991
j7		D. F. Wong, Edward M. Reingold: Probabilistic Analysis of a Grouping Algorithm. Algorithmica 6(2): 192-206 (1991)
j6		Khe-Sing The, Martin D. F. Wong, Jason Cong: A layout modification approach to via minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 10(4): 536-541 (1991)
j5		Yang Cai, Martin D. F. Wong: Optimal channel pin assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 10(11): 1413-1424 (1991)
j4		Martin D. F. Wong, Mohankumar Guruswamy: Channel ordering for VLSI layout with rectilinear modules. IEEE Trans. on CAD of Integrated Circuits and Systems 10(11): 1425-1431 (1991)
j3		Yang Cai, Martin D. F. Wong: Channel/switchbox definition for VLSI building-block layout. IEEE Trans. on CAD of Integrated Circuits and Systems 10(12): 1485-1493 (1991)
c17		Yang Cai, D. F. Wong: On Minimizing the Number of L-Shaped Channels. DAC 1991: 328-334
c16		Mohankumar Guruswamy, D. F. Wong: A General Multi-Layer Area Router. DAC 1991: 335-340
c15		T. W. Her, D. F. Wong: Optimal Module Implementation and Its Application to Transistor Placement. ICCAD 1991: 98-101
c14		Yang Cai, D. F. Wong: Minimizing Channel Density by Shifting Blocks and Terminals. ICCAD 1991: 524-527
c13		John C. Chan, Baxter F. Womack, D. F. Wong: On the Manisfestation of Faults to Errors in Signature Analysis. ICCD 1991: 360-363
c12		Khe-Sing The, D. F. Wong: Area Optimization for Higher Order Hierarchical Floorplans. ICCD 1991: 520-523
	1990
c11		Ting-Chi Wang, D. F. Wong: An Optimal Algorithm for Floorplan Area Optimization. DAC 1990: 180-186
c10		Yang Cai, D. F. Wong: A Channel/Switchbox Definition Algorithm for Building-Block Layout. DAC 1990: 638-641
c9		Yang Cai, D. F. Wong: Optimal via-shifting in channel compaction. EURO-DAC 1990: 186-190
c8		Shinichiro Haruyama, D. F. Wong, Donald S. Fussell: Topological Routing Using Geometric Information. ICCAD 1990: 6-9
c7		Yang Cai, D. F. Wong: An Optimal Channel Pin Assignment Algorithm. ICCAD 1990: 10-13
c6		T. W. Her, D. F. Wong, T. H. Freeman: Optimal Orientations of Transistor Chains. ICCAD 1990: 524-527
	1989
j2		D. F. Wong, C. L. Liu: Floorplan Design of VLSI Circuits. Algorithmica 4(2): 263-291 (1989)
c5		D. F. Wong, P. S. Sakhamuri: Efficient Floorplan Area Optimization. DAC 1989: 586-589
c4		Khe-Sing The, D. F. Wong, Jason Cong: VIA Minimization by Layout Modification. DAC 1989: 799-802
	1988
j1		Jason Cong, Martin D. F. Wong, C. L. Liu: A new approach to three- or four-layer channel routing. IEEE Trans. on CAD of Integrated Circuits and Systems 7(10): 1094-1104 (1988)
c3		Jingsheng Cong, D. F. Wong: How to Obtain More Compactable Channel Routing Solutions. DAC 1988: 663-666
	1987
c2		D. F. Wong, C. L. Liu: Array Optimization for VLSI Synthesis. DAC 1987: 537-543
	1986
c1		D. F. Wong, C. L. Liu: A new algorithm for floorplan design. DAC 1986: 101-107

Coauthor Index