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T. Watanabe
2010 – today
- 2010
[c14]T. Watanabe: Manipulability measures taking necessary joint torques for grasping into consideration. IROS 2010: 598-603- [c13]Shinya Kimura, T. Watanabe, Yasumichi Aiyama: Force based manipulation of Jenga blocks. IROS 2010: 4287-4292
2000 – 2009
- 2002
- [c12]Tsuyoshi Isshiki, Akihisa Ohta, T. Watanabe, T. Nakada, K. Akahane, I. Sisla, Dongju Li, Hiroaki Kunieda: High density bit-serial FPGA with LUT embedding shift register function. APCCAS (1) 2002: 475-480
- [c11]Jie Huang, K. Kume, A. Saji, M. Nishihashi, T. Watanabe, William L. Martens: Robotic Spatial Sound Localization and Its 3-D Sound Human Interface. CW 2002: 191-200
- [c10]I. Hattori, A. Kamo, T. Watanabe, H. Asai: Optimal placement of decoupling capacitors on PCB using Poynting vectors obtained by FDTD method. ISCAS (5) 2002: 29-32
- [c9]H. Kubota, A. Kamo, T. Watanabe, H. Asai: Noise analysis of power/ground planes on PCB by SPICE-like simulator with model order reduction technique. ISCAS (5) 2002: 649-552
1990 – 1999
- 1999
- [c8]T. Watanabe, A. Mori: RORP: Distributed object relocation protocol for wide area networks. IPCCC 1999: 217-224
- [c7]A. Kamo, T. Watanabe, H. Asai: Expanded GMC for transient analysis of transmission line networks. ISCAS (6) 1999: 33-36
- [c6]E. Miuno, T. Abaashi, T. Watanabe: Extracting nonplanar connections in a terminal-vertex graph. ISCAS (6) 1999: 121-124
- [c5]T. Watanabe, H. Asai: Efficient synthesis technique of time-domain models for interconnects having 3-D structures based on FDTD method. ISCAS (6) 1999: 266-269
- 1997
- [c4]Kazuhiro Ozawa, T. Watanabe, Masayasu Kanke: Fuzzy auto-regressive model and its applications. KES (1) 1997: 112-117
1980 – 1989
- 1989
- [c3]T. Watanabe, H. Matsumoto, P. D. Tannenbaum: Hardware technology and architecture of the NEC SX-3/SX-X supercomputer system. SC 1989: 842-846
- 1987
- [j3]T. Watanabe, S. G. Monanty: On an inclusion-exclusion formula based on the reflection principle. Discrete Mathematics 64(2-3): 281-288 (1987)
- [j2]T. Watanabe, H. Kitazawa, Y. Sugiyama: A Parallel Adaptable Routing Algorithm and its Implementation on a Two-Dimensional Array Processor. IEEE Trans. on CAD of Integrated Circuits and Systems 6(2): 241-250 (1987)
- 1986
- [c2]T. Watanabe, T. Masuishi, T. Nishiyama, N. Horie: Knowledge-based optimal IIL generator from conventional logic circuit descriptions. DAC 1986: 608-614
- [c1]K. Murano, Hideo Kuwahara, T. Watanabe, K. Ohta, H. Gambe, T. Gotohda, H. Takaoka: A Processor VLSI for Multiplexing and Circuit Termination Functions - MUX Processor. ICC 1986: 1674-1678
- 1983
- [j1]T. Watanabe, Makoto Endo, N. Miyahara: A New Automatic Logic Interconnection Verification System for VLSI Design. IEEE Trans. on CAD of Integrated Circuits and Systems 2(2): 70-82 (1983)
Coauthor Index
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last updated on 2013-05-07 01:01 CEST by the dblp team