Katsumasa Watanabe

Tomoya Suzuki, Shigeru Yamashita, Masaki Nakanishi, Katsumasa Watanabe: Robust Quantum Algorithms Computing OR with epsilon-Biased Oracles. IEICE Transactions 90-D(2): 395-402 (2007)

Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita, Kazuo Nakajima, Katsumasa Watanabe: An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs. IEICE Transactions 89-A(12): 3416-3426 (2006)

Tomoya Suzuki, Shigeru Yamashita, Masaki Nakanishi, Katsumasa Watanabe: Robust Quantum Algorithms with epsilon-Biased Oracles. COCOON 2006: 116-125

Mitsuru Tomono, Masaki Nakanishi, Katsumasa Watanabe, Shigeru Yamashita: Event-oriented computing with reconfigurable platform. ASP-DAC 2005: 1248-1251

Nobuo Nakai, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe: Reconfigurable 1-Bit Processor Array with Reduced Wirng Area. ERSA 2005: 225-234

Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe: A real-time 64-monosyllable recognition LSI with learning mechanism. ASP-DAC 2001: 31-32

Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe: Speech recognition chip for monosyllables. ASP-DAC 2001: 396-399

Shinji Kimura, Hiroyuki Kida, Kazuyoshi Takagi, Tatsumori Abematsu, Katsumasa Watanabe: An application specific Java processor with reconfigurabilities. ASP-DAC 2000: 25-26

Kazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, Katsumasa Watanabe: Multi-clock path analysis using propositional satisfiability. ASP-DAC 2000: 81-86

Kazuhiro Nakamura, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe: Waiting false path analysis of sequential logic circuits for performance optimization. ICCAD 1998: 392-395

Shinji Kimura, Yasufumi Itou, Makoto Hirao, Katsumasa Watanabe, Mitsuteru Yukishita, Akira Nagoya: A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor. CODES 1997: 147-152

Tatsuo Tsuji, Katsumasa Watanabe, Athushi Ikehata: Structured FORTRAN Preprocessors Generating Optimized Output. Softw., Pract. Exper. 18(5): 427-442 (1988)