Chi-Chao Wang

Anupama R. Subramaniam, Ritu Singhal, Chi-Chao Wang, Yu Cao: Leakage reduction through optimization of regular layout parameters. Microelectronics Journal 43(1): 25-33 (2012)

Chi-Chao Wang, Yun Ye, Yu Cao: The potential of Fe-FET for robust design under variations: A compact modeling study. Microelectronics Journal 43(11): 898-903 (2012)

Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Chi-Chao Wang, Frank Liu, Sani R. Nassif, Yu Cao: Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation. IEEE Trans. VLSI Syst. 18(4): 666-670 (2010)

Yun Ye, Chi-Chao Wang, Yu Cao: Simulation of random telegraph Noise with 2-stage equivalent circuit. ICCAD 2010: 709-713

Jungseob Lee, Chi-Chao Wang, Hamid Reza Ghasemi, Lloyd Bircher, Yu Cao, Nam Sung Kim: Workload-adaptive process tuning strategy for power-efficient multi-core processors. ISLPED 2010: 225-230

Yu Cao, Asha Balijepalli, Saurabh Sinha, Chi-Chao Wang, Wenping Wang, Wei Zhao: The Predictive Technology Model in the Late Silicon Era and Beyond. Foundations and Trends in Electronic Design Automation 3(4): 305-401 (2009)

Xia Li, Wei Zhao, Yu Cao, Zhi Zhu, Jooyoung Song, David Bang, Chi-Chao Wang, Seung H. Kang, Joseph Wang, Matt Nowak, Nick Yu: Pathfinding for 22nm CMOS designs using Predictive Technology Models. CICC 2009: 227-230

Chi-Chao Wang, Wei Zhao, Frank Liu, Min Chen, Yu Cao: Modeling of layout-dependent stress effect in CMOS design. ICCAD 2009: 513-520

Anupama R. Subramaniam, Ritu Singhal, Chi-Chao Wang, Yu Cao: Design rule optimization of regular layout for leakage reduction in nanoscale design. ASP-DAC 2008: 474-479