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Zvonko G. Vranesic
2000 – 2009
- 2009
[c35]Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown: Enhancements to FPGA design methodology using streaming. FPL 2009: 294-301- 2008
- [c34]Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown: Towards Compilation of Streaming Programs into FPGA Hardware. FDL 2008: 67-72
- 2007
- [c33]Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown: On Digital Search Trees - A Simple Method for Constructing Balanced Binary Trees. ICSOFT (PL/DPS/KE/MUSE) 2007: 61-68
- 2006
- [j29]Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic: Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2331-2340 (2006)
- [c32]Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown: A Multithreaded Soft Processor for SoPC Area Reduction. FCCM 2006: 131-142
- [c31]Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic: Adaptive FPGAs: High-Level Architecture and a Synthesis Method. FPL 2006: 1-8
- 2005
- [c30]Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown: Experiences with Soft-Core Processor Design. IPDPS 2005
- 2003
- [j28]Debatosh Debnath, Zvonko G. Vranesic: A fast algorithm for OR-AND-OR synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1166-1176 (2003)
- 2002
- [j27]Zeljko Zilic, Zvonko G. Vranesic: A Deterministic Multivariate Interpolation Algorithm for Small Finite Fields. IEEE Trans. Computers 51(9): 1100-1105 (2002)
- [c29]Valavan Manohararajah, Terry P. Borer, Stephen Dean Brown, Zvonko G. Vranesic: Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. FPL 2002: 232-241
- 2001
- [j26]Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic: Structural analysis and generation of synthetic digital circuits with memory. IEEE Trans. VLSI Syst. 9(1): 223-226 (2001)
- 2000
- [c28]R. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic: The NUMAchine Multiprocessor. ICPP 2000: 487-496
1990 – 1999
- 1999
- [j25]Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic: The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning. International Journal of Parallel Programming 27(5): 327-356 (1999)
- [j24]Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic: The memory/logic interface in FPGAs with large embedded memory arrays. IEEE Trans. VLSI Syst. 7(1): 80-91 (1999)
- 1998
- [j23]Zeljko Zilic, Zvonko G. Vranesic: Using Decision Diagrams to Design ULMs for FPGAs. IEEE Trans. Computers 47(9): 970-982 (1998)
- [c27]A. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic: Design and Implementation of the NUMAchine Multiprocessor. DAC 1998: 66-69
- [c26]
- 1997
- [j22]Sinisa Srbljic, Zvonko G. Vranesic, Michael Stumm, Leo Budin: Analytical Prediction of Performance for Cache Coherence Protocols. IEEE Trans. Computers 46(11): 1155-1173 (1997)
- [c25]Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic: Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays. FPGA 1997: 10-16
- [c24]Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic: Memory-System Design Considerations for Dynamically-Scheduled Processors. ISCA 1997: 133-143
- [c23]Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic: The Multicluster Architecture: Reducing Cycle Time Through Partitioning. MICRO 1997: 149-159
- 1996
- [j21]Stephen Dean Brown, Muhammad M. Khellah, Zvonko G. Vranesic: Minimizing FPGA Interconnect Delays. IEEE Design & Test of Computers 13(4): 16-23 (1996)
- [c22]Stephen Dean Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic: Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. DAC 1996: 427-432
- [c21]
- [c20]Zeljko Zilic, Zvonko G. Vranesic: New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms. ISMVL 1996: 16-23
- 1995
- [j20]Zeljko Zilic, Zvonko G. Vranesic: A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions. IEEE Trans. Computers 44(8): 1012-1020 (1995)
- [j19]Keith I. Farkas, Zvonko G. Vranesic, Michael Stumm: Scalable cache consistency for hierarchically structured multiprocessors. The Journal of Supercomputing 8(4): 345-369 (1995)
- [c19]Muhammad Jaseemuddin, Zvonko G. Vranesic: Bidirectional Ring: An Alternative to the Hierarchy of Unidirectional Rings. Euro-Par 1995: 567-578
- [c18]Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic: Architecture of Centralized Field-Configurable Memory. FPGA 1995: 97-103
- [c17]Zeljko Zilic, Zvonko G. Vranesic: Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation. ISMVL 1995: 36-43
- 1994
- [c16]Sinisa Srbljic, Zvonko G. Vranesic, Leo Budin: Performance Prediction for Different Consistency Schemes in Distributed Shared Memory Systems. HPDC 1994: 295-302
- [c15]Alireza Kaviani, Zvonko G. Vranesic: On Scheduling in Multiprocessor Systems Using Fuzzy Logic. ISMVL 1994: 141-147
- 1993
- [j18]Michiel van de Panne, Eugene Fiume, Zvonko G. Vranesic: Physically Based Modeling and Control of Turning. CVGIP: Graphical Model and Image Processing 55(6): 507-521 (1993)
- [j17]Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic: A stochastic model to predict the routability of field-programmable gate arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1827-1838 (1993)
- [c14]
- [c13]Steven J. E. Wilton, Zvonko G. Vranesic: Architectural Support for Block Transfers in a Shared-Memory Multiprocessor. SPDP 1993: 51-55
- 1992
- [j16]Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic: A detailed router for field-programmable gate arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 620-628 (1992)
- [c12]Konrad Lei, Zvonko G. Vranesic: Towards the Realization of 4-Valued CMOS Circuits. ISMVL 1992: 104-110
- [c11]Keith I. Farkas, Zvonko G. Vranesic, Michael Stumm: Cache Consistency in Hierarchical-Ring-Based Multiprocessors. SC 1992: 348-357
- 1991
- [j15]Zvonko G. Vranesic, Michael Stumm, David M. Lewis, Ron White: Hector: A Hierarchically Structured Shared-memory Multiprocessor. IEEE Computer 24(1): 72-79 (1991)
- [j14]Mostafa H. Abd-El-Barr, Zvonko G. Vranesic, Safwat G. Zaky: Algorithmic Synthesis of MVL Functions for CCD Implementation. IEEE Trans. Computers 40(8): 977-986 (1991)
- [c10]Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic: Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs. DAC 1991: 227-233
- [c9]Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic: Technology Mapping on Lookup Table-Based FPGAs for Performance. ICCAD 1991: 568-571
- [c8]Zvonko G. Vranesic, V. Carl Hamacher, A. K. Sanwalka, Safwat G. Zaky: A Hybrid Token/Insertion Ring LAN. INFOCOM 1991: 211-220
- [c7]Konrad Lei, Zvonko G. Vranesic: On the Synthesis of 4-Valued Current Mode CMOS Circuits. ISMVL 1991: 147-155
- [e1]Zvonko G. Vranesic (Ed.): Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, Canada, May, 27-30 1991. ACM 1991, ISBN 0-89791-394-9
- 1990
- [j13]Mostafa H. Abd-El-Barr, Zvonko G. Vranesic: Cost Reduction in the CCD Realization of MVMT Function. IEEE Trans. Computers 39(5): 702-706 (1990)
- [c6]Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic: A Detailed Router for Field-Programmable Gate Arrays. ICCAD 1990: 382-385
- [c5]Lap-kong Chan, Zvonko G. Vranesic: TORMLAN - A Multichannel Local Area Network Protocol. INFOCOM 1990: 756-765
- [c4]Safwat G. Zaky, Zvonko G. Vranesic, Mostafa H. Abd-El-Barr: Step-Wise Synthesis of CCD MVL Functions. ISMVL 1990: 300-307
- [c3]Michiel van de Panne, Eugene Fiume, Zvonko G. Vranesic: Reusable motion synthesis using state-space controllers. SIGGRAPH 1990: 225-234
1980 – 1989
- 1988
- [j12]Jonathan Rose, W. Martin Snelgrove, Zvonko G. Vranesic: Parallel standard cell placement algorithms with quality equivalent to simulated annealing. IEEE Trans. on CAD of Integrated Circuits and Systems 7(3): 387-396 (1988)
- 1986
- [j11]Wayne M. Loucks, William I. Kwak, Zvonko G. Vranesic: Implementation of a Dynamic Address Assignment Protocol in a Local Area Network. Computer Networks 11: 133-146 (1986)
- [j10]Mostafa H. Abd-El-Barr, Safwat G. Zaky, Zvonko G. Vranesic: Synthesis of Multivalued Multithreshold Functions for CCD Implementation. IEEE Trans. Computers 35(2): 124-133 (1986)
- 1984
- [j9]Kuang-Wei Chiang, Zvonko G. Vranesic: Comments on ``Fault Diagnosis of MOS Combinational Networks''. IEEE Trans. Computers 33(10): 947 (1984)
- 1983
- [j8]Kuang-Wei Chiang, Zvonko G. Vranesic: A Tree Representation of Combinational Networks. IEEE Trans. Computers 32(3): 315-319 (1983)
- [j7]Paul Chow, Zvonko G. Vranesic, Jui Lin Yen: A Pipelined Distributed Arithmetic PFFT Processor. IEEE Trans. Computers 32(12): 1128-1136 (1983)
- [c2]
- 1981
- [j6]C. L. Lam, Zvonko G. Vranesic: Key compression using segment strings. Inf. Syst. 6(2): 139-146 (1981)
- 1980
- [j5]H. T. Mouftah, Kenneth C. Smith, Zvonko G. Vranesic: Ternary Rate-Multipliers. IEEE Trans. Computers 29(10): 929-931 (1980)
1970 – 1979
- 1978
- [j4]A. Druzeta, Zvonko G. Vranesic: A. Higher Radix Technique for Fault Detection in Many-Valued Multithreshold Networks. IEEE Trans. Computers 27(11): 1070-1073 (1978)
- 1977
- [j3]Zvonko G. Vranesic: Multiple-Valued Logic: An Introduction and Overview. IEEE Trans. Computers 26(12): 1181-1182 (1977)
- 1973
- [c1]Zvonko G. Vranesic, V. Carl Hamacher, Y. Y. Leung: Design of a Fully Variable - Length Structured Minicomputer. ISCA 1973: 251-255
- 1972
- [j2]Zvonko G. Vranesic, V. Carl Hamacher: Ternary logic in parallel multipliers. Comput. J. 15(3): 254-258 (1972)
- 1970
- [j1]K. M. Waliuzzaman, Zvonko G. Vranesic: On Decomposition of Multi-Valued Switching Functions. Comput. J. 13(4): 359-362 (1970)
Coauthor Index
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last updated on 2013-02-01 22:58 CET by the dblp team