Jörg E. Vollrath

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	2006
c10		Zaid Al-Ars, Said Hamdioui, A. J. van de Goor, Georgi Gaydadjiev, Jörg E. Vollrath: DRAM-Specific Space of Memory Tests. ITC 2006: 1-10
c9		Jörg E. Vollrath, Jürg Schwizer, Marcin Gnat, Ralf Schneider, Bret Johnson: DDR2 DRAM Output Timing Optimization. MTDT 2006: 49-54
	2005
c8		Zaid Al-Ars, Said Hamdioui, Jörg E. Vollrath: Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach. Asian Test Symposium 2005: 434-439
	2003
j2		Jörg E. Vollrath: Testing and Characterization of SDRAMs. IEEE Design & Test of Computers 20(1): 42-50 (2003)
c7		Jörg E. Vollrath: Output Timing Measurement Using an Idd Method. MTDT 2003: 43-46
	2002
c6		Jörg E. Vollrath: Signal Margin Analysis for Memory Sense Amplifiers . DELTA 2002: 123-127
	2001
j1		Jörg E. Vollrath, Ulf Lederer, Thomas Hladschik: Compressed Bit Fail Maps for Memory Fail Pattern Classification. J. Electronic Testing 17(3-4): 291-297 (2001)
c5		Jörg E. Vollrath, Randall Rooney: Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment. ITC 2001: 768-775
	2000
c4		Jörg E. Vollrath: Synchronous Dynamic Memory Test Construction: A Field Approach. MTDT 2000: 59-64
	1999
c3		Jörg E. Vollrath: Tutorial: Characterizing SDRAMS. MTDT 1999: 62-
	1998
c2		Jörg E. Vollrath, Markus Huebl, Ernst Stahl: Power Analysis of DRAMs. Asian Test Symposium 1998: 334-339
	1997
c1		Jörg E. Vollrath: Cell Signal Measurement for High-Density DRAMs. ITC 1997: 209-216

Coauthor Index

1	Zaid Al-Ars	[c10] [c8]
2	Georgi Gaydadjiev (Georgi Nedeltchev Gaydadjiev)	[c10]
3	Marcin Gnat	[c9]
4	A. J. van de Goor	[c10]
5	Said Hamdioui	[c10] [c8]
6	Thomas Hladschik	[j1]
7	Markus Huebl	[c2]
8	Bret Johnson	[c9]
9	Ulf Lederer	[j1]
10	Randall Rooney	[c5]
11	Ralf Schneider	[c9]
12	Jürg Schwizer	[c9]
13	Ernst Stahl	[c2]

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