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Arnaud Virazel
2010 – today
- 2013
[j19]Aida Todri, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel: A Study of Tapered 3-D TSVs for Power and Thermal Integrity. IEEE Trans. VLSI Syst. 21(2): 306-319 (2013)- [j18]Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel: Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation. IEEE Trans. VLSI Syst. 21(5): 958-970 (2013)
- [c70]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine: Test solution for data retention faults in low-power SRAMs. DATE 2013: 442-447
- [c69]Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Etienne Auvray: Effect-cause intra-cell diagnosis at transistor level. ISQED 2013: 460-467
- 2012
- [j17]Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez: Analysis and Fault Modeling of Actual Resistive Defects in ATMEL [InlineMediaObject not available: see fulltext.] eFlash Memories. J. Electronic Testing 28(2): 215-228 (2012)
- [j16]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes. J. Electronic Testing 28(3): 317-329 (2012)
- [c68]J. Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, G. Prenat, Jérémy Alvarez-Herault, Ken Mackay: Impact of Resistive-Bridge Defects in TAS-MRAM Architectures. Asian Test Symposium 2012: 125-130
- [c67]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, P. Debaud, S. Guilhot: Power Supply Noise Sensor Based on Timing Uncertainty Measurements. Asian Test Symposium 2012: 161-166
- [c66]Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel: Why and How Controlling Power Consumption during Test: A Survey. Asian Test Symposium 2012: 221-226
- [c65]J. Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, G. Prenat, Jérémy Alvarez-Herault, Ken Mackay: Impact of resistive-open defects on the heat current of TAS-MRAM architectures. DATE 2012: 532-537
- [c64]J. Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, G. Prenat, Jérémy Alvarez-Herault, Ken Mackay: Coupling-based resistive-open defects in TAS-MRAM architectures. European Test Symposium 2012: 1
- [c63]C. Metzler, Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel: Through-Silicon-Via resistive-open defect analysis. European Test Symposium 2012: 1
- [c62]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine: Defect analysis in power mode control logic of low-power SRAMs. European Test Symposium 2012: 1
- [c61]Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Antoine D. Touboul, Frederic Wrobel, Frédéric Saigné: Evaluation of test algorithms stress effect on SRAMs under neutron radiation. IOLTS 2012: 121-122
- [c60]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine: Low-power SRAMs power mode control logic: Failure analysis and test solutions. ITC 2012: 1-10
- [c59]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Michael E. Imhof, Hans-Joachim Wunderlich: A pseudo-dynamic comparator for error detection in fault tolerant architectures. VTS 2012: 50-55
- [c58]Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel: Advanced test methods for SRAMs. VTS 2012: 300-301
- 2011
- [c57]Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel: Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. Asian Test Symposium 2011: 90-95
- [c56]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich: A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Asian Test Symposium 2011: 136-141
- [c55]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Nabil Badereddine: Failure Analysis and Test Solutions for Low-Power SRAMs. Asian Test Symposium 2011: 459-460
- [c54]Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Kohei Miyase, X. Wen: Power-Aware Test Pattern Generation for At-Speed LOS Testing. Asian Test Symposium 2011: 506-510
- [c53]Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel: A study of path delay variations in the presence of uncorrelated power and ground supply noise. DDECS 2011: 189-194
- [c52]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling. DDECS 2011: 353-358
- [c51]Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez: On using a SPICE-like TSTAC™ eFlash model for design and test. DDECS 2011: 359-364
- [c50]Luigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel: Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector. DFT 2011: 294-301
- [c49]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda: A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. European Test Symposium 2011: 153-158
- [c48]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: On using address scrambling to implement defect tolerance in SRAMs. ITC 2011: 1-8
- 2010
- [j15]Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed: A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes. J. Low Power Electronics 6(2): 359-374 (2010)
- [j14]Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel: A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects. IEEE Trans. Computers 59(3): 289-300 (2010)
- [c47]Paolo Rech, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Luigi Dilillo: A Memory Fault Simulator for Radiation-Induced Effects in SRAMs. Asian Test Symposium 2010: 100-105
- [c46]Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer: A Comprehensive System-on-Chip Logic Diagnosis. Asian Test Symposium 2010: 237-242
- [c45]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: A statistical simulation method for reliability analysis of SRAM core-cells. DAC 2010: 853-856
- [c44]Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen: Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes. DDECS 2010: 376-381
- [c43]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: Impact of Resistive-Bridging Defects in SRAM Core-Cell. DELTA 2010: 265-269
- [c42]Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez: A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction. European Test Symposium 2010: 81-86
- [c41]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. European Test Symposium 2010: 132-137
- [c40]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: Setting test conditions for improving SRAM reliability. European Test Symposium 2010: 257
- [c39]Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed: Is test power reduction through X-filling good enough? ITC 2010: 805
- [c38]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich: Parity prediction synthesis for nano-electronic gate designs. ITC 2010: 820
- [c37]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: Detecting NBTI induced failures in SRAM core-cells. VTS 2010: 75-80
2000 – 2009
- 2009
- [j13]Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash. J. Electronic Testing 25(2-3): 127-144 (2009)
- [j12]Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Is triple modular redundancy suitable for yield improvement? IET Computers & Digital Techniques 3(6): 581-592 (2009)
- [j11]Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Analysis of Resistive-Open Defects in SRAM Sense Amplifiers. IEEE Trans. VLSI Syst. 17(10): 1556-1559 (2009)
- [c36]Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer: Delay Fault Diagnosis in Sequential Circuits. Asian Test Symposium 2009: 355-360
- [c35]Alexandre Ney, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin: A new design-for-test technique for SRAM core-cell stability faults. DATE 2009: 1344-1348
- [c34]Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute: Comprehensive bridging fault diagnosis based on the SLAT paradigm. DDECS 2009: 264-269
- [c33]Youssef Benabboud, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute: A case study on logic diagnosis for System-on-Chip. ISQED 2009: 253-259
- [c32]Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard: NAND flash testing: A preliminary study on actual defects. ITC 2009: 1
- 2008
- [j10]Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault: A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction. J. Electronic Testing 24(4): 353-364 (2008)
- [c31]Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin: A Design-for-Diagnosis Technique for SRAM Write Drivers. DATE 2008: 1480-1485
- [c30]Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Improving Diagnosis Resolution without Physical Information. DELTA 2008: 210-215
- [c29]Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Using TMR Architectures for Yield Improvement. DFT 2008: 7-15
- [c28]Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Yield Improvement, Fault-Tolerance to the Rescue?. IOLTS 2008: 165-166
- [c27]Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs. ITC 2008: 1-10
- [c26]Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: SoC Yield Improvement: Redundant Architectures to the Rescue? ITC 2008: 1
- [c25]Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin: An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing. VTS 2008: 89-94
- 2007
- [j9]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits. J. Electronic Testing 23(5): 435-444 (2007)
- [c24]Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Slow write driver faults in 65nm SRAM technology: analysis and March test solution. DATE 2007: 528-533
- [c23]Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: A Mixed Approach for Unified Logic Diagnosis. DDECS 2007: 239-242
- [c22]Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: DERRIC: A Tool for Unified Logic Diagnosis. European Test Symposium 2007: 13-20
- [c21]Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. European Test Symposium 2007: 77-84
- [c20]Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. European Test Symposium 2007: 97-104
- [c19]Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Jean Michel Daga: A concurrent approach for testing address decoder faults in eFlash memories. ITC 2007: 1-10
- [c18]Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. VTS 2007: 47-52
- [c17]Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. VTS 2007: 361-368
- 2006
- [j8]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: A Gated Clock Scheme for Low Power Testing of Logic Cores. J. Electronic Testing 22(1): 89-99 (2006)
- [j7]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan: ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. J. Electronic Testing 22(3): 287-296 (2006)
- [c16]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. DDECS 2006: 256-261
- [c15]Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich: Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. VLSI-SoC 2006: 403-408
- [c14]Olivier Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: An Overview of Failure Mechanisms in Embedded Flash Memories. VTS 2006: 108-113
- 2005
- [j6]Simone Borri, Magali Bastian Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel: Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. J. Electronic Testing 21(2): 169-179 (2005)
- [j5]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan: Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. J. Electronic Testing 21(5): 551-561 (2005)
- [c13]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. DAC 2005: 857-862
- [c12]Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault: Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. PATMOS 2005: 540-549
- [c11]Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault: Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. VLSI-SoC 2005: 267-281
- [c10]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan: Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. VTS 2005: 183-188
- 2004
- [c9]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan: Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. Asian Test Symposium 2004: 266-271
- [c8]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Design of Routing-Constrained Low Power Scan Chains. DATE 2004: 62-67
- [c7]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Design of Routing-Constrained Low Power Scan Chains. DELTA 2004: 287-294
- [c6]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri: March iC-: An Improved Version of March C- for ADOFs Detection. VTS 2004: 129-138
- 2003
- [c5]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri: Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. Asian Test Symposium 2003: 250-255
- 2002
- [j4]Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich: High Defect Coverage with Low-Power Test Sequences in a BIST Environment. IEEE Design & Test of Computers 19(5): 44-52 (2002)
- [j3]René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Hardware Generation of Random Single Input Change Test Sequences. J. Electronic Testing 18(2): 145-157 (2002)
- [c4]René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: On Using Efficient Test Sequences for BIST. VTS 2002: 145-152
- 2001
- [j2]Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences. J. Electronic Testing 17(3-4): 233-241 (2001)
- [c3]René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Random Adjacent Sequences: An Efficient Solution for Logic BIST. VLSI-SOC 2001: 413-424
- 2000
- [c2]Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. IOLTW 2000: 121-126
1990 – 1999
- 1999
- [j1]Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel: A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. J. Electronic Testing 14(1-2): 95-102 (1999)
- 1998
- [c1]Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel: A BIST Structure to Test Delay Faults in a Scan Environment. Asian Test Symposium 1998: 435-439
Coauthor Index
[j19] [j18] [c70] [c69] [j17] [j16] [c68] [c67] [c66] [c65] [c64] [c63] [c62] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [j15] [j14] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [j12] [c36] [c34] [c33] [c32] [c30] [c29] [c28] [c27] [c26] [c23] [c22]
[j19] [j18] [c70] [c69] [j17] [j16] [c68] [c67] [c66] [c65] [c64] [c63] [c62] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [j15] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c32] [c27] [j9] [j7] [c16] [j6] [j5] [c13] [c10] [c9] [c6] [c5]
[j19] [j18] [c70] [c69] [j17] [j16] [c68] [c67] [c66] [c65] [c64] [c63] [c62] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [j15] [j14] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [j13] [j12] [j11] [c36] [c35] [c34] [c33] [c32] [j10] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [j9] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [j8] [j7] [c16] [c15] [c14] [j6] [j5] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [j4] [j3] [c4] [j2] [c3] [c2] [j1] [c1]
[j17] [j16] [c58] [c56] [c55] [c53] [c52] [c51] [c50] [c49] [c48] [j15] [j14] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [j13] [j12] [j11] [c36] [c35] [c34] [c33] [c32] [j10] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [j9] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [j8] [j7] [c16] [c15] [c14] [j6] [j5] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [j4] [j3] [c4] [j2] [c3] [c2] [j1] [c1]
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last updated on 2013-06-11 12:20 CEST by the dblp team