DBLP: Massimo Violante

	2012
c90		Salvatore Campagna, Massimo Violante: An hybrid architecture to detect transient faults in microprocessors: An experimental validation. DATE 2012: 1433-1438
c89		Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Marco Ottavi, Salvatore Pontarelli, Adelio Salsano, Cecilia Metra, Martin Omaña, Daniele Rossi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Simone Gerardin, M. Bagatin, Alessandro Paccagnella: High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies. DFT 2012: 121-125
	2011
b2		Niccolò Battezzati, Luca Sterpone, Massimo Violante: Reconfigurable Field Programmable Gate Arrays for Mission-Critical Applications. Springer 2011, isbn 978-1-4419-7594-2, pp. I-VII, 1-220
j17		Hipólito Guzmán-Miranda, Luca Sterpone, Massimo Violante, Miguel A. Aguirre, Manuel Gutiérrez-Rizo: Coping With the Obsolescence of Safety- or Mission-Critical Embedded Systems Using FPGAs. IEEE Transactions on Industrial Electronics 58(3): 814-821 (2011)
j16		Massimo Violante, Cristina Meinhardt, Ricardo Reis, Matteo Sonza Reorda: A Low-Cost Solution for Deploying Processor Cores in Harsh Environments. IEEE Transactions on Industrial Electronics 58(7): 2617-2626 (2011)
c88		Salvatore Campagna, Moazzam Hussain, Massimo Violante: A Light-Weight Fault Tolerance Framework for Space Computing using COTS Components. ARCS Workshops 2011
c87		Enrico Costenaro, Massimo Violante, Dan Alexandrescu: A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories. IOLTS 2011: 49-54
	2010
j15		Gianpiero Cabodi, Marco Murciano, Massimo Violante: Boosting software fault injection for dependability analysis of real-time embedded applications. ACM Trans. Embedded Comput. Syst. 10(2): 24 (2010)
c86		Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Niccolò Battezzati, Luca Sterpone, Massimo Violante: An integrated flow for the design of hardened circuits on SRAM-based FPGAs. European Test Symposium 2010: 214-219
c85		Salvatore Campagna, Massimo Violante: A framework to support the design of COTS-based reliable space computers for on-board data handling. IOLTS 2010: 91-96
c84		Niccolò Battezzati, Davide Serrone, Massimo Violante: A new framework for the automatic insertion of mitigation structures in circuits netlists. IOLTS 2010: 190-191
c83		Niccolò Battezzati, Luca Sterpone, Massimo Violante, Filomena Decuzzi: A new software tool for static analysis of SET sensitiveness in Flash-based FPGAs. VLSI-SoC 2010: 79-84
	2009
c82		Matteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis: A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips. DATE 2009: 352-357
c81		Francesco Abate, Luca Sterpone, Massimo Violante, Fernanda Lima Kastensmidt: A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs. DATE 2009: 1226-1229
c80		Matteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis: An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs. DFT 2009: 254-262
c79		Niccolò Battezzati, Filomena Decuzzi, Luca Sterpone, Massimo Violante: Soft errors in Flash-based FPGAs: Analysis methodologies and first results. FPL 2009: 723-724
c78		Massimo Violante, M. L. Esposti: A low-cost solution for developing reliable Linux-based space computers for on-board data handling. IOLTS 2009: 49-54
c77		Niccolò Battezzati, Filomena Decuzzi, Massimo Violante, Michel Briet: Application-oriented SEU sensitiveness analysis of Atmel rad-hard FPGAs. IOLTS 2009: 89-94
c76		Gianpaolo Macario, Marco Torchiano, Massimo Violante: An in-vehicle infotainment software architecture based on google android. SIES 2009: 257-260
	2008
j14		Cristiana Bolchini, Antonio Miele, Fabio Rebaudengo, Fabio Salice, Donatella Sciuto, Luca Sterpone, Massimo Violante: Software and Hardware Techniques for SEU Detection in IP Processors. J. Electronic Testing 24(1-3): 35-44 (2008)
j13		Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante: Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs. J. Electronic Testing 24(1-3): 45-56 (2008)
c75		Francesco Abate, Massimo Violante: Coping with Obsolescence of Processor Cores in Critical Applications. DFT 2008: 24-32
c74		Niccolò Battezzati, Simone Gerardin, Andrea Manuzzato, Alessandro Paccagnella, Sana Rezgui, Luca Sterpone, Massimo Violante: On the Evaluation of Radiation-Induced Transient Faults in Flash-Based FPGAs. IOLTS 2008: 135-140
	2007
j12		Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro: Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs. J. Electronic Testing 23(1): 47-54 (2007)
c73		Andrea Manuzzato, Paolo Rech, Simone Gerardin, Alessandro Paccagnella, Luca Sterpone, Massimo Violante: Sensitivity Evaluation of TMR-Hardened Circuits to Multiple SEUs Induced by Alpha Particles in Commercial SRAM-Based FPGAs. DFT 2007: 79-86
c72		Salvatore Pontarelli, Luca Sterpone, Gian-Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante: Optimization of Self Checking FIR filters by means of Fault Injection Analysis. DFT 2007: 96-104
c71		Luca Sterpone, Massimo Violante: Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs. European Test Symposium 2007: 159-164
c70		Luca Sterpone, Massimo Violante: A new decompression system for the configuration process of SRAM-based FPGAS. ACM Great Lakes Symposium on VLSI 2007: 241-246
c69		Luca Sterpone, Massimo Violante: A new hardware architecture for performing the gridding of DNA microarray images. ACM Great Lakes Symposium on VLSI 2007: 341-346
c68		Marco Murciano, Massimo Violante: Validating the dependability of embedded systems through fault injection by means of loadable kernel modules. HLDVT 2007: 179-186
c67		Salvatore Pontarelli, Luca Sterpone, Gian-Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante: Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders. IOLTS 2007: 194-196
	2006
b1		Olga Goloubeva, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Software-Implemented Hardware Fault Tolerance. Springer 2006, isbn 978-0-387-26060-0, pp. I-XI, 1-224
j11		Julio Pérez Acle, Matteo Sonza Reorda, Massimo Violante: Early, Accurate Dependability Analysis of CAN-Based Networked Systems. IEEE Design & Test of Computers 23(1): 38-45 (2006)
j10		Luca Sterpone, Massimo Violante: Hardening FPGA-based Systems Against SEUs: A New Design Methodology. JCP 1(1): 22-30 (2006)
j9		Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante: A New Hybrid Fault Detection Technique for Systems-on-a-Chip. IEEE Trans. Computers 55(2): 185-198 (2006)
j8		Luca Sterpone, Massimo Violante: A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs. IEEE Trans. Computers 55(6): 732-744 (2006)
c66		Maurizio Martina, Guido Masera, Andrea Molino, Fabrizio Vacca, Luca Sterpone, Massimo Violante: A new approach to compress the configuration information of programmable devices. DATE Designers' Forum 2006: 48-51
c65		Luca Sterpone, Massimo Violante: ReCoM: A New Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications. DDECS 2006: 54-58
c64		Maurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto: Combined software and hardware techniques for the design of reliable IP processors. DFT 2006: 265-273
c63		Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante: Online hardening of programs against SEUs and SETs. DFT 2006: 280-290
c62		Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena: Fault Injection-based Reliability Evaluation of SoPCs. European Test Symposium 2006: 75-82
c61		Luca Sterpone, Massimo Violante: Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices. IOLTS 2006: 189-190
c60		Matteo Sonza Reorda, Massimo Violante: Hardware-in-the-Loop-Based Dependability Analysis of Automotive Systems. IOLTS 2006: 229-234
c59		Paolo Bernardi, Leticia Maria Veiras Bolzani, Alberto Manzone, Marcella Guagliumi Massimo Osella, Massimo Violante, Matteo Sonza Reorda: Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications. MTV 2006: 3-8
	2005
c58		Luca Sterpone, Massimo Violante: A design flow for protecting FPGA-based systems against single event upsets. DFT 2005: 436-444
c57		Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors. DFT 2005: 445-453
c56		Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante: On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core. DSN 2005: 50-58
c55		Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero, Luca Sterpone, Massimo Violante: New evolutionary techniques for test-program generation for complex microprocessor cores. GECCO 2005: 2193-2194
c54		Matteo Sonza Reorda, Luca Sterpone, Massimo Violante: Efficient Estimation of SEU Effects in SRAM-Based FPGAs. IOLTS 2005: 54-59
c53		Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante: Automatic generation of test sets for SBST of microprocessor IP cores. SBCCI 2005: 74-79
	2004
j7		Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: A New Approach to Software-Implemented Fault Tolerance. J. Electronic Testing 20(4): 433-437 (2004)
j6		Matteo Sonza Reorda, Massimo Violante: A New Approach to the Analysis of Single Event Transients in VLSI Circuits. J. Electronic Testing 20(5): 511-521 (2004)
j5		Matteo Sonza Reorda, Massimo Violante: Efficient analysis of single event transients. Journal of Systems Architecture 50(5): 239-246 (2004)
c52		Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante: Automatic Generation of Validation Stimuli for Application-Specific Processors. DATE 2004: 188-193
c51		M. Bellato, Paolo Bernardi, D. Bortolato, A. Candelori, M. Ceschia, Alessandro Paccagnella, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, P. Zambolin: Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA. DATE 2004: 584-589
c50		Matteo Sonza Reorda, Massimo Violante: On-Line Analysis and Perturbation of CAN Networks. DFT 2004: 424-432
c49		Ernesto Sánchez, Giovanni Squillero, Massimo Violante: Exploiting HW Acceleration for Classifying Complex Test Program Generation Problems. EvoWorkshops 2004: 230-239
c48		Fulvio Corno, Julio Pérez Acle, Mattia Ramasso, Matteo Sonza Reorda, Massimo Violante: Validation of the dependability of CAN-based networked systems. HLDVT 2004: 161-164
c47		Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante: Hybrid Soft Error Detection by Means of Infrastructure IP Cores. IOLTS 2004: 79-88
c46		Paolo Bernardi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante: On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs. IOLTS 2004: 115-120
c45		Fulvio Corno, Julio Pérez Acle, Matteo Sonza Reorda, Massimo Violante: A multi-level approach to the dependability analysis of networked systems based on the CAN protocol. SBCCI 2004: 71-75
	2003
j4		Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor. J. Electronic Testing 19(5): 577-584 (2003)
j3		Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: New techniques for efficiently assessing reliability of SOCs. Microelectronics Journal 34(1): 53-61 (2003)
c44		Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor. DATE 2003: 10602-10607
c43		Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories. DATE 2003: 10720-10725
c42		Abdelaziz Ammari, Régis Leveugle, Matteo Sonza Reorda, Massimo Violante: Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels. DFT 2003: 336-343
c41		J. Pérez, Matteo Sonza Reorda, Massimo Violante: Dependability Analysis of CAN Networks: An Emulation-Based Approach. DFT 2003: 537-
c40		Olga Goloubeva, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Soft-Error Detection Using Control Flow Assertions. DFT 2003: 581-588
c39		Matteo Sonza Reorda, Massimo Violante: Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits. FPL 2003: 616-626
c38		Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante: High-level test generation for hardware testing and software validation. HLDVT 2003: 143-148
c37		Matteo Sonza Reorda, Massimo Violante: Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits. IOLTS 2003: 101-105
c36		Massimo Violante, M. Ceschia, Matteo Sonza Reorda, Alessandro Paccagnella, Paolo Bernardi, Maurizio Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori: Analyzing SEU Effects in SRAM-based FPGAs. IOLTS 2003: 119-123
c35		Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante: An RT-level Concurrent Error Detection Technique for Data Dominated Systems. IOLTS 2003: 159
c34		Davide Appello, Paolo Bernardi, Alessandra Fudoli, Maurizio Rebaudengo, Matteo Sonza Reorda, Vincenzo Tancorre, Massimo Violante: Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores. ITC 2003: 379-385
c33		J. Pérez, Matteo Sonza Reorda, Massimo Violante: Accurate Dependability Analysis of CAN-Based Networked Systems. SBCCI 2003: 337-342
	2002
j2		Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits. J. Electronic Testing 18(3): 261-271 (2002)
c32		Pierluigi Civera, Luca Macchiarulo, Massimo Violante: A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis. DFT 2002: 31-39
c31		Matteo Sonza Reorda, Massimo Violante: Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments. DFT 2002: 263-274
c30		Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: A New Functional Fault Model for FPGA Application-Oriented Testing. DFT 2002: 372-380
c29		Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs. FPL 2002: 607-615
c28		Matteo Sonza Reorda, Massimo Violante, Nicola Mazzocca, Salvatore Venticinque, Andrea Bobbio, Giuliana Franceschinis: A hierarchical approach for designing dependable systems. HLDVT 2002: 63-68
c27		Gert Jervan, Zebo Peng, Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante: High-level and hierarchical test sequence generation. HLDVT 2002: 169-174
c26		Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Analysis of SEU Effects in a Pipelined Processor. IOLTW 2002: 112-116
	2001
c25		Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: FPGA-Based Fault Injection for Microprocessor Systems. Asian Test Symposium 2001: 304-
c24		Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante: On the test of microprocessor IP cores. DATE 2001: 209-213
c23		Ph. Cheynet, B. Nicolescu, Raoul Velazco, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: System safety through automatic high-level code transformations: an experimental evaluation. DATE 2001: 297-301
c22		Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits . DFT 2001: 250-258
c21		Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits. FPL 2001: 493-502
c20		Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Exploiting FPGA for Accelerating Fault Injection Experiments. IOLTW 2001: 9-13
c19		Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Marco Torchiano: A Source-to-Source Compiler for Generating Dependable Software. SCAM 2001: 35-44
c18		Marcello Lajolo, Matteo Sonza Reorda, Massimo Violante: Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs. VLSI Design 2001: 371-
	2000
c17		Marcello Lajolo, Luciano Lavagno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Automatic test bench generation for simulation-based validation. CODES 2000: 136-140
c16		Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno: Evaluating System Dependability in a Co-Design Framework. DATE 2000: 586-590
c15		Maurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante: An Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications. DFT 2000: 257-265
c14		Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Prediction of Power Requirements for High-Speed Circuits. EvoWorkshops 2000: 247-254
c13		Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno: Behavioral-level test vector generation for system-on-chip designs. HLDVT 2000: 21-26
c12		Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante: A genetic algorithm-based system for generating test programs for microprocessor IP cores. ICTAI 2000: 195-198
c11		Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Ph. Cheynet, B. Nicolescu, Raoul Velazco: Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures. IOLTW 2000: 17-
c10		B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: New Techniques for Accelerating Fault Injection in VHDL Descriptions. IOLTW 2000: 61-66
c9		Marcello Lajolo, Luciano Lavagno, Matteo Sonza Reorda, Massimo Violante: Early Power Estimation for System-on-Chip Designs. PATMOS 2000: 108-117
c8		B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Speeding-Up Fault Injection Campaigns in VHDL Models. SAFECOMP 2000: 27-36
c7		Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante: Low Power BIST via Non-Linear Hybrid Cellular Automata. VTS 2000: 29-34
	1999
j1		Fulvio Corno, Uwe Gläser, Paolo Prinetto, Matteo Sonza Reorda, Heinrich Theodor Vierhaus, Massimo Violante: SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information. IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 191-202 (1999)
c6		Maurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante: Soft-Error Detection through Software Fault-Tolerance Techniques. DFT 1999: 210-218
c5		Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaudengo, Massimo Violante: Optimal Vector Selection for Low Power BIST. DFT 1999: 219-226
c4		Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Test Pattern Generation Under Low Power Constraints. EvoWorkshops 1999: 162-170
c3		Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: ALPS: A Peak Power Estimation Tool for Sequential Circuits. Great Lakes Symposium on VLSI 1999: 350-353
	1998
c2		Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante: Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection. DATE 1998: 670-677
	1997
c1		Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG. Asian Test Symposium 1997: 68-73

2012

c90

Salvatore Campagna, Massimo Violante: An hybrid architecture to detect transient faults in microprocessors: An experimental validation. DATE 2012: 1433-1438

c89

Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Marco Ottavi, Salvatore Pontarelli, Adelio Salsano, Cecilia Metra, Martin Omaña, Daniele Rossi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Simone Gerardin, M. Bagatin, Alessandro Paccagnella: High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies. DFT 2012: 121-125

2011

Niccolò Battezzati, Luca Sterpone, Massimo Violante: Reconfigurable Field Programmable Gate Arrays for Mission-Critical Applications. Springer 2011, isbn 978-1-4419-7594-2, pp. I-VII, 1-220

j17

Hipólito Guzmán-Miranda, Luca Sterpone, Massimo Violante, Miguel A. Aguirre, Manuel Gutiérrez-Rizo: Coping With the Obsolescence of Safety- or Mission-Critical Embedded Systems Using FPGAs. IEEE Transactions on Industrial Electronics 58(3): 814-821 (2011)

j16

Massimo Violante, Cristina Meinhardt, Ricardo Reis, Matteo Sonza Reorda: A Low-Cost Solution for Deploying Processor Cores in Harsh Environments. IEEE Transactions on Industrial Electronics 58(7): 2617-2626 (2011)

c88

Salvatore Campagna, Moazzam Hussain, Massimo Violante: A Light-Weight Fault Tolerance Framework for Space Computing using COTS Components. ARCS Workshops 2011

c87

Enrico Costenaro, Massimo Violante, Dan Alexandrescu: A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories. IOLTS 2011: 49-54

2010

j15

Gianpiero Cabodi, Marco Murciano, Massimo Violante: Boosting software fault injection for dependability analysis of real-time embedded applications. ACM Trans. Embedded Comput. Syst. 10(2): 24 (2010)

c86

Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Niccolò Battezzati, Luca Sterpone, Massimo Violante: An integrated flow for the design of hardened circuits on SRAM-based FPGAs. European Test Symposium 2010: 214-219

c85

Salvatore Campagna, Massimo Violante: A framework to support the design of COTS-based reliable space computers for on-board data handling. IOLTS 2010: 91-96

c84

Niccolò Battezzati, Davide Serrone, Massimo Violante: A new framework for the automatic insertion of mitigation structures in circuits netlists. IOLTS 2010: 190-191

c83

Niccolò Battezzati, Luca Sterpone, Massimo Violante, Filomena Decuzzi: A new software tool for static analysis of SET sensitiveness in Flash-based FPGAs. VLSI-SoC 2010: 79-84

2009

c82

Matteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis: A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips. DATE 2009: 352-357

c81

Francesco Abate, Luca Sterpone, Massimo Violante, Fernanda Lima Kastensmidt: A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs. DATE 2009: 1226-1229

c80

Matteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis: An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs. DFT 2009: 254-262

c79

Niccolò Battezzati, Filomena Decuzzi, Luca Sterpone, Massimo Violante: Soft errors in Flash-based FPGAs: Analysis methodologies and first results. FPL 2009: 723-724

c78

Massimo Violante, M. L. Esposti: A low-cost solution for developing reliable Linux-based space computers for on-board data handling. IOLTS 2009: 49-54

c77

Niccolò Battezzati, Filomena Decuzzi, Massimo Violante, Michel Briet: Application-oriented SEU sensitiveness analysis of Atmel rad-hard FPGAs. IOLTS 2009: 89-94

c76

Gianpaolo Macario, Marco Torchiano, Massimo Violante: An in-vehicle infotainment software architecture based on google android. SIES 2009: 257-260

2008

j14

Cristiana Bolchini, Antonio Miele, Fabio Rebaudengo, Fabio Salice, Donatella Sciuto, Luca Sterpone, Massimo Violante: Software and Hardware Techniques for SEU Detection in IP Processors. J. Electronic Testing 24(1-3): 35-44 (2008)

j13

Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante: Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs. J. Electronic Testing 24(1-3): 45-56 (2008)

c75

Francesco Abate, Massimo Violante: Coping with Obsolescence of Processor Cores in Critical Applications. DFT 2008: 24-32

c74

Niccolò Battezzati, Simone Gerardin, Andrea Manuzzato, Alessandro Paccagnella, Sana Rezgui, Luca Sterpone, Massimo Violante: On the Evaluation of Radiation-Induced Transient Faults in Flash-Based FPGAs. IOLTS 2008: 135-140

2007

j12

Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro: Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs. J. Electronic Testing 23(1): 47-54 (2007)

c73

Andrea Manuzzato, Paolo Rech, Simone Gerardin, Alessandro Paccagnella, Luca Sterpone, Massimo Violante: Sensitivity Evaluation of TMR-Hardened Circuits to Multiple SEUs Induced by Alpha Particles in Commercial SRAM-Based FPGAs. DFT 2007: 79-86

c72

Salvatore Pontarelli, Luca Sterpone, Gian-Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante: Optimization of Self Checking FIR filters by means of Fault Injection Analysis. DFT 2007: 96-104

c71

Luca Sterpone, Massimo Violante: Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs. European Test Symposium 2007: 159-164

c70

Luca Sterpone, Massimo Violante: A new decompression system for the configuration process of SRAM-based FPGAS. ACM Great Lakes Symposium on VLSI 2007: 241-246

c69

Luca Sterpone, Massimo Violante: A new hardware architecture for performing the gridding of DNA microarray images. ACM Great Lakes Symposium on VLSI 2007: 341-346

c68

Marco Murciano, Massimo Violante: Validating the dependability of embedded systems through fault injection by means of loadable kernel modules. HLDVT 2007: 179-186

c67

Salvatore Pontarelli, Luca Sterpone, Gian-Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante: Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders. IOLTS 2007: 194-196

2006

Olga Goloubeva, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Software-Implemented Hardware Fault Tolerance. Springer 2006, isbn 978-0-387-26060-0, pp. I-XI, 1-224

j11

Julio Pérez Acle, Matteo Sonza Reorda, Massimo Violante: Early, Accurate Dependability Analysis of CAN-Based Networked Systems. IEEE Design & Test of Computers 23(1): 38-45 (2006)

j10

Luca Sterpone, Massimo Violante: Hardening FPGA-based Systems Against SEUs: A New Design Methodology. JCP 1(1): 22-30 (2006)

Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante: A New Hybrid Fault Detection Technique for Systems-on-a-Chip. IEEE Trans. Computers 55(2): 185-198 (2006)

Luca Sterpone, Massimo Violante: A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs. IEEE Trans. Computers 55(6): 732-744 (2006)

c66

Maurizio Martina, Guido Masera, Andrea Molino, Fabrizio Vacca, Luca Sterpone, Massimo Violante: A new approach to compress the configuration information of programmable devices. DATE Designers' Forum 2006: 48-51

c65

Luca Sterpone, Massimo Violante: ReCoM: A New Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications. DDECS 2006: 54-58

c64

Maurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto: Combined software and hardware techniques for the design of reliable IP processors. DFT 2006: 265-273

c63

Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante: Online hardening of programs against SEUs and SETs. DFT 2006: 280-290

c62

Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena: Fault Injection-based Reliability Evaluation of SoPCs. European Test Symposium 2006: 75-82

c61

Luca Sterpone, Massimo Violante: Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices. IOLTS 2006: 189-190

c60

Matteo Sonza Reorda, Massimo Violante: Hardware-in-the-Loop-Based Dependability Analysis of Automotive Systems. IOLTS 2006: 229-234

c59

Paolo Bernardi, Leticia Maria Veiras Bolzani, Alberto Manzone, Marcella Guagliumi Massimo Osella, Massimo Violante, Matteo Sonza Reorda: Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications. MTV 2006: 3-8

2005

c58

Luca Sterpone, Massimo Violante: A design flow for protecting FPGA-based systems against single event upsets. DFT 2005: 436-444

c57

Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors. DFT 2005: 445-453

c56

Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante: On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core. DSN 2005: 50-58

c55

Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero, Luca Sterpone, Massimo Violante: New evolutionary techniques for test-program generation for complex microprocessor cores. GECCO 2005: 2193-2194

c54

Matteo Sonza Reorda, Luca Sterpone, Massimo Violante: Efficient Estimation of SEU Effects in SRAM-Based FPGAs. IOLTS 2005: 54-59

c53

Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante: Automatic generation of test sets for SBST of microprocessor IP cores. SBCCI 2005: 74-79

2004

Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: A New Approach to Software-Implemented Fault Tolerance. J. Electronic Testing 20(4): 433-437 (2004)

Matteo Sonza Reorda, Massimo Violante: A New Approach to the Analysis of Single Event Transients in VLSI Circuits. J. Electronic Testing 20(5): 511-521 (2004)

Matteo Sonza Reorda, Massimo Violante: Efficient analysis of single event transients. Journal of Systems Architecture 50(5): 239-246 (2004)

c52

Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante: Automatic Generation of Validation Stimuli for Application-Specific Processors. DATE 2004: 188-193

c51

M. Bellato, Paolo Bernardi, D. Bortolato, A. Candelori, M. Ceschia, Alessandro Paccagnella, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, P. Zambolin: Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA. DATE 2004: 584-589

c50

Matteo Sonza Reorda, Massimo Violante: On-Line Analysis and Perturbation of CAN Networks. DFT 2004: 424-432

c49

Ernesto Sánchez, Giovanni Squillero, Massimo Violante: Exploiting HW Acceleration for Classifying Complex Test Program Generation Problems. EvoWorkshops 2004: 230-239

c48

Fulvio Corno, Julio Pérez Acle, Mattia Ramasso, Matteo Sonza Reorda, Massimo Violante: Validation of the dependability of CAN-based networked systems. HLDVT 2004: 161-164

c47

Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante: Hybrid Soft Error Detection by Means of Infrastructure IP Cores. IOLTS 2004: 79-88

c46

Paolo Bernardi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante: On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs. IOLTS 2004: 115-120

c45

Fulvio Corno, Julio Pérez Acle, Matteo Sonza Reorda, Massimo Violante: A multi-level approach to the dependability analysis of networked systems based on the CAN protocol. SBCCI 2004: 71-75

2003

Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor. J. Electronic Testing 19(5): 577-584 (2003)

Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: New techniques for efficiently assessing reliability of SOCs. Microelectronics Journal 34(1): 53-61 (2003)

c44

Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor. DATE 2003: 10602-10607

c43

Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories. DATE 2003: 10720-10725

c42

Abdelaziz Ammari, Régis Leveugle, Matteo Sonza Reorda, Massimo Violante: Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels. DFT 2003: 336-343

c41

J. Pérez, Matteo Sonza Reorda, Massimo Violante: Dependability Analysis of CAN Networks: An Emulation-Based Approach. DFT 2003: 537-

c40

Olga Goloubeva, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Soft-Error Detection Using Control Flow Assertions. DFT 2003: 581-588

c39

Matteo Sonza Reorda, Massimo Violante: Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits. FPL 2003: 616-626

c38

Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante: High-level test generation for hardware testing and software validation. HLDVT 2003: 143-148

c37

Matteo Sonza Reorda, Massimo Violante: Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits. IOLTS 2003: 101-105

c36

Massimo Violante, M. Ceschia, Matteo Sonza Reorda, Alessandro Paccagnella, Paolo Bernardi, Maurizio Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori: Analyzing SEU Effects in SRAM-based FPGAs. IOLTS 2003: 119-123

c35

Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante: An RT-level Concurrent Error Detection Technique for Data Dominated Systems. IOLTS 2003: 159

c34

Davide Appello, Paolo Bernardi, Alessandra Fudoli, Maurizio Rebaudengo, Matteo Sonza Reorda, Vincenzo Tancorre, Massimo Violante: Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores. ITC 2003: 379-385

c33

J. Pérez, Matteo Sonza Reorda, Massimo Violante: Accurate Dependability Analysis of CAN-Based Networked Systems. SBCCI 2003: 337-342

2002

Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits. J. Electronic Testing 18(3): 261-271 (2002)

c32

Pierluigi Civera, Luca Macchiarulo, Massimo Violante: A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis. DFT 2002: 31-39

c31

Matteo Sonza Reorda, Massimo Violante: Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments. DFT 2002: 263-274

c30

Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: A New Functional Fault Model for FPGA Application-Oriented Testing. DFT 2002: 372-380

c29

Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs. FPL 2002: 607-615

c28

Matteo Sonza Reorda, Massimo Violante, Nicola Mazzocca, Salvatore Venticinque, Andrea Bobbio, Giuliana Franceschinis: A hierarchical approach for designing dependable systems. HLDVT 2002: 63-68

c27

Gert Jervan, Zebo Peng, Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante: High-level and hierarchical test sequence generation. HLDVT 2002: 169-174

c26

Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Analysis of SEU Effects in a Pipelined Processor. IOLTW 2002: 112-116

2001

c25

Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: FPGA-Based Fault Injection for Microprocessor Systems. Asian Test Symposium 2001: 304-

c24

Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante: On the test of microprocessor IP cores. DATE 2001: 209-213

c23

Ph. Cheynet, B. Nicolescu, Raoul Velazco, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: System safety through automatic high-level code transformations: an experimental evaluation. DATE 2001: 297-301

c22

Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits . DFT 2001: 250-258

c21

Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits. FPL 2001: 493-502

c20

Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Exploiting FPGA for Accelerating Fault Injection Experiments. IOLTW 2001: 9-13

c19

Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Marco Torchiano: A Source-to-Source Compiler for Generating Dependable Software. SCAM 2001: 35-44

c18

Marcello Lajolo, Matteo Sonza Reorda, Massimo Violante: Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs. VLSI Design 2001: 371-

2000

c17

Marcello Lajolo, Luciano Lavagno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Automatic test bench generation for simulation-based validation. CODES 2000: 136-140

c16

Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno: Evaluating System Dependability in a Co-Design Framework. DATE 2000: 586-590

c15

Maurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante: An Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications. DFT 2000: 257-265

c14

Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Prediction of Power Requirements for High-Speed Circuits. EvoWorkshops 2000: 247-254

c13

Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno: Behavioral-level test vector generation for system-on-chip designs. HLDVT 2000: 21-26

c12

Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante: A genetic algorithm-based system for generating test programs for microprocessor IP cores. ICTAI 2000: 195-198

c11

Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Ph. Cheynet, B. Nicolescu, Raoul Velazco: Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures. IOLTW 2000: 17-

c10

B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: New Techniques for Accelerating Fault Injection in VHDL Descriptions. IOLTW 2000: 61-66

Marcello Lajolo, Luciano Lavagno, Matteo Sonza Reorda, Massimo Violante: Early Power Estimation for System-on-Chip Designs. PATMOS 2000: 108-117

B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Speeding-Up Fault Injection Campaigns in VHDL Models. SAFECOMP 2000: 27-36

Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante: Low Power BIST via Non-Linear Hybrid Cellular Automata. VTS 2000: 29-34

1999

Fulvio Corno, Uwe Gläser, Paolo Prinetto, Matteo Sonza Reorda, Heinrich Theodor Vierhaus, Massimo Violante: SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information. IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 191-202 (1999)

Maurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante: Soft-Error Detection through Software Fault-Tolerance Techniques. DFT 1999: 210-218

Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaudengo, Massimo Violante: Optimal Vector Selection for Low Power BIST. DFT 1999: 219-226

Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Test Pattern Generation Under Low Power Constraints. EvoWorkshops 1999: 162-170

Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: ALPS: A Peak Power Estimation Tool for Sequential Circuits. Great Lakes Symposium on VLSI 1999: 350-353

1998

Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante: Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection. DATE 1998: 670-677

1997

Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG. Asian Test Symposium 1997: 68-73

1	Francesco Abate	[c81] [c75]
2	Julio Pérez Acle	[j11] [c48] [c45]
3	Miguel A. Aguirre (M. A. Aguirre)	[j17]
4	Dan Alexandrescu	[c87]
5	Abdelaziz Ammari	[c42]
6	Davide Appello	[c34]
7	M. Bagatin	[c89]
8	Niccolò Battezzati	[b2] [c86] [c84] [c83] [c79] [c77] [c74]
9	M. Bellato	[c51] [c36]
10	Paolo Bernardi	[j9] [c59] [c57] [c56] [c51] [c46] [c43] [c36] [c34]
11	Andrea Bobbio	[c28]
12	Cristiana Bolchini	[c89] [c86] [j14] [c64]
13	Leticia Maria Veiras Bolzani (Leticia Maria Veiras Bolzani Poehls)	[j9] [c59] [c57] [c56] [c47]
14	D. Bortolato	[c51] [c36]
15	Michel Briet	[c77]
16	Gianpiero Cabodi	[j15]
17	Salvatore Campagna	[c90] [c88] [c85]
18	A. Candelori	[c51] [c36]
19	Gian-Carlo Cardarilli	[c72] [c67]
20	Luigi Carro	[j13] [j12] [c63]
21	M. Ceschia	[c51] [c36]
22	Ph. Cheynet	[c23] [c11]
23	Pierluigi Civera	[j3] [j2] [c32] [c25] [c22] [c21] [c20]
24	Fulvio Corno	[c48] [c45] [c24] [c14] [c12] [c7] [j1] [c5] [c4] [c3] [c2] [c1]
25	Enrico Costenaro	[c87]
26	Filomena Decuzzi	[c83] [c79] [c77]
27	Luis Entrena (Luis Entrena-Arrontes)	[c62]
28	M. L. Esposti	[c78]
29	Giuliana Franceschinis	[c28]
30	Alessandra Fudoli	[c34]
31	Simone Gerardin	[c89] [c74] [c73]
32	Uwe Gläser	[j1]
33	Olga Goloubeva	[b1] [c52] [c40] [c38] [c35] [c27]
34	Manuel Gutiérrez-Rizo	[j17]
35	Hipólito Guzmán-Miranda	[j17]
36	Moazzam Hussain	[c88]
37	Gert Jervan	[c27]
38	Fernanda Gusmão de Lima Kastensmidt (Fernanda Gusmão de Lima, Fernanda Lima Kastensmidt)	[c81] [j12]
39	Marcello Lajolo	[c18] [c17] [c16] [c13] [c9]
40	Luciano Lavagno	[c17] [c16] [c13] [c9]
41	Régis Leveugle	[c42]
42	Carlos Arthur Lang Lisbôa	[j13] [c63]
43	Celia López-Ongil (Celia López)	[c62]
44	Gianpaolo Macario	[c76]
45	Luca Macchiarulo	[j3] [j2] [c32] [c25] [c22] [c21] [c20]
46	Andrea Manuzzato	[c74] [c73]
47	Alberto Manzone	[c59]
48	Maurizio Martina	[c66]
49	Guido Masera	[c66]
50	Nicola Mazzocca	[c28]
51	Cristina Meinhardt	[j16] [c82] [c80]
52	Cecilia Metra	[c89]
53	Antonio Miele	[c89] [c86] [j14] [c64]
54	Andrea Molino	[c66]
55	Marco Murciano	[j15] [c68]
56	B. Nicolescu	[c23] [c11]
57	Martin Omaña	[c89]
58	Marcella Guagliumi Massimo Osella	[c59]
59	Marco Ottavi	[c89]
60	Alessandro Paccagnella	[c89] [c74] [c73] [c51] [c36]
61	B. Parrotta	[c10] [c8]
62	Zebo Peng	[c27]
63	Salvatore Pontarelli	[c89] [c72] [c67]
64	Marta Portela-García	[c62]
65	Paolo Prinetto	[j1] [c2] [c1]
66	J. Pérez	[c41] [c33]
67	Mattia Ramasso	[c48]
68	Marco Re	[c72] [c67]
69	Fabio Rebaudengo	[j14]
70	Maurizio Rebaudengo	[b1] [j9] [c64] [c57] [c56] [j7] [c51] [c47] [j4] [j3] [c44] [c43] [c40] [c36] [c34] [j2] [c30] [c29] [c26] [c25] [c23] [c22] [c21] [c20] [c19] [c17] [c16] [c15] [c14] [c13] [c11] [c10] [c8] [c7] [c6] [c5] [c4] [c3] [c1]
71	Paolo Rech	[c73]
72	Ricardo Augusto da Luz Reis (Ricardo A. L. Reis, Ricardo Reis)	[j16] [c82] [c80]
73	Matteo Sonza Reorda	[c89] [j16] [c82] [c80] [j13] [j12] [c72] [c67] [b1] [j11] [j9] [c63] [c62] [c60] [c59] [c57] [c56] [c55] [c54] [c53] [j7] [j6] [j5] [c52] [c51] [c50] [c48] [c47] [c46] [c45] [j4] [j3] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [j2] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [j1] [c6] [c5] [c4] [c3] [c2] [c1]
74	Sana Rezgui	[c74]
75	Eduardo Luis Rhod	[j13]
76	Daniele Rossi	[c89]
77	Fabio Salice	[j14]
78	Adelio Salsano	[c89] [c72] [c67]
79	Chiara Sandionigi	[c89] [c86]
80	Massimiliano Schillaci	[c55]
81	Donatella Sciuto	[j14] [c64]
82	Davide Serrone	[c84]
83	Giovanni Squillero	[c55] [c53] [c49] [c24] [c12] [c7]
84	Luca Sterpone	[c89] [b2] [j17] [c86] [c83] [c81] [c79] [j14] [c74] [j12] [c73] [c72] [c71] [c70] [c69] [c67] [j10] [j8] [c66] [c65] [c64] [c62] [c61] [c58] [c55] [c54] [c46]
85	Ernesto Sánchez (Edgar E. Sánchez, Edgar Ernesto Sánchez Sánchez)	[c55] [c53] [c49]
86	Vincenzo Tancorre	[c34]
87	Marco Torchiano	[c76] [c19] [c15] [c6]
88	Fabrizio Vacca	[c66]
89	Fabian Vargas	[j9] [c56] [c47]
90	Raoul Velazco	[c23] [c11]
91	Salvatore Venticinque	[c28]
92	Heinrich Theodor Vierhaus	[j1]
93	P. Zambolin	[c51] [c36]

Massimo Violante

Coauthor Index