| 2010 | ||
|---|---|---|
| c9 | Arpad Gellert, Gianluca Palermo, Vittorio Zaccaria, Adrian Florea, Lucian N. Vintan, Cristina Silvano: Energy-performance design space exploration in SMT architectures exploiting selective load value predictions. DATE 2010: 271-274 | |
| 2009 | ||
| j3 | Arpad Gellert, Adrian Florea, Lucian N. Vintan: Exploiting selective instruction reuse and value prediction in a superscalar architecture. Journal of Systems Architecture - Embedded Systems Design 55(3): 188-195 (2009) | |
| 2007 | ||
| c8 | Arpad Gellert, Adrian Florea, Maria N. Vintan, Colin Egan, Lucian N. Vintan: Unbiased Branches: An Open Problem. Asia-Pacific Computer Systems Architecture Conference 2007: 16-27 | |
| c7 | Michael F. P. O'Boyle, François Bodin, José González, Lucian N. Vintan: Topic 4 High-Performance Architectures and Compilers. Euro-Par 2007: 235 | |
| 2006 | ||
| c6 | Lucian N. Vintan, Arpad Gellert, Adrian Florea, Marius Oancea, Colin Egan: Understanding Prediction Limits Through Unbiased Branches. Asia-Pacific Computer Systems Architecture Conference 2006: 480-487 | |
| 2003 | ||
| j2 | Colin Egan, Gordon L. Steven, Patrick Quick, Rubén Anguera, Fleur L. Steven, Lucian N. Vintan: Two-level branch prediction using neural networks. Journal of Systems Architecture 49(12-15): 557-570 (2003) | |
| j1 | Lucian N. Vintan, Marius Sbera, Ioan Z. Mihu, Adrian Florea: An alternative to branch prediction: pre-computed branches. SIGARCH Computer Architecture News 31(3): 20-29 (2003) | |
| 2002 | ||
| c5 | Colin Egan, Gordon Steven, Lucian N. Vintan: Cached Two-Level Adaptive Branch Predictors with Multiple Stages. ARCS 2002: 179-194 | |
| 2001 | ||
| c4 | Gordon B. Steven, Rubén Anguera, Colin Egan, Fleur L. Steven, Lucian N. Vintan: Dynamic Branch Prediction Using Neural Networks. DSD 2001: 178-185 | |
| c3 | Colin Egan, Gordon Steven, Won Shim, Lucian N. Vintan: Applying Caching to Two-Level Adaptive Branch Prediction. DSD 2001: 186-193 | |
| 1999 | ||
| c2 | Lucian N. Vintan, Colin Egan: Extending Correlation in Branch Prediction Schemes. EUROMICRO 1999: 1441-1448 | |
| c1 | Lucian N. Vintan, Cristian Armat, Gordon B. Steven: The impact of cache organisation on the instruction issue rate of a superscalar processor. PDP 1999: 58-65 | |
Colors in the list of coauthors
Last update Sat May 25 15:00:58 2013 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page