Vijaykrishnan Narayanan
List of publications from the DBLP Bibliography Server - FAQ
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 | 2013 | |
|---|---|---|
| j73 |      | Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan: A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays. JETC 9(1): 5 (2013) |
| j72 | | Ahmed Al-Maashri, Matthew Cotter, Nandhini Chandramoorthy, Michael DeBole, Chi-Li Yu, Vijaykrishnan Narayanan, Chaitali Chakrabarti: Hardware Acceleration for Neuromorphic Vision Algorithms. Signal Processing Systems 70(2): 163-175 (2013) |
| c235 | | Yuan-Ying Chang, Yoshi Shih-Chieh Huang, Vijaykrishnan Narayanan, Chung-Ta King: ShieldUS: A novel design of dynamic shielding for eliminating 3D TSV crosstalk coupling noise. ASP-DAC 2013: 675-680 |
| c234 | | Yang Xiao, Kevin M. Irick, Vijaykrishnan Narayanan, Donghwa Shin, Naehyuck Chang: Saliency aware display power management. DATE 2013: 1203-1208 |
| c233 | | Chang-En Chiang, Li-Fu Tang, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan: On reconfigurable single-electron transistor arrays synthesis using reordering techniques. DATE 2013: 1807-1812 |
| c232 | | |
| 2012 | ||
| j71 | | Shengqi Yang, Pallav Gupta, Marilyn Wolf, Dimitrios N. Serpanos, Vijaykrishnan Narayanan, Yuan Xie: Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling. ACM Trans. Embedded Comput. Syst. 11(3): 62 (2012) |
| j70 | | Padmaraj Singh, Vijaykrishnan Narayanan, David L. Landis: Targeted random test generation for power-aware multicore designs. ACM Trans. Design Autom. Electr. Syst. 17(3): 25 (2012) |
| c231 | | Sungho Park, Yong Cheol Peter Cho, Kevin M. Irick, Vijaykrishnan Narayanan: A reconfigurable platform for the design and verification of domain-specific accelerators. ASP-DAC 2012: 108-113 |
| c230 | | Karthik Swaminathan, Raghav Pisolkar, Cong Xu, Vijaykrishnan Narayanan: When to forget: A system-level perspective on STT-RAMs. ASP-DAC 2012: 311-316 |
| c229 | | Jagdish Sabarad, Srinidhi Kestur, Sun-Mi Park, Dharav Dantara, Vijaykrishnan Narayanan, Yang Chen, Deepak Khosla: A reconfigurable accelerator for neuromorphic object recognition. ASP-DAC 2012: 813-818 |
| c228 | | Emre Kultursay, Karthik Swaminathan, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta: Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores. CODES+ISSS 2012: 245-254 |
| c227 | | Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Ravishankar Iyer, Chita R. Das: Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs. DAC 2012: 243-252 |
| c226 | | Ahmed Al-Maashri, Michael DeBole, Matthew Cotter, Nandhini Chandramoorthy, Yang Xiao, Vijaykrishnan Narayanan, Chaitali Chakrabarti: Accelerating neuromorphic vision algorithms for recognition. DAC 2012: 579-584 |
| c225 | | Padmaraj Singh, Vijaykrishnan Narayanan, David L. Landis: Hazard driven test generation for SMT processors. DATE 2012: 256-259 |
| c224 | | Sun-Mi Park, Srinidhi Kestur, Jagdish Sabarad, Vijaykrishnan Narayanan, Mary Jane Irwin: An FPGA-based accelerator for cortical object classification. DATE 2012: 691-696 |
| c223 | | Srinidhi Kestur, Sun-Mi Park, Jagdish Sabarad, Dharav Dantara, Vijaykrishnan Narayanan, Yang Chen, Deepak Khosla: Emulating Mammalian Vision on Reconfigurable Hardware. FCCM 2012: 141-148 |
| c222 | | Jing Xie, Vijaykrishnan Narayanan, Yuan Xie: Mitigating electromigration of power supply networks using bidirectional current stress. ACM Great Lakes Symposium on VLSI 2012: 299-302 |
| c221 | | Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir: Design space exploration of workload-specific last-level caches. ISLPED 2012: 243-248 |
| c220 | | Ravindhiran Mukundrajan, Matthew Cotter, Vinay Saripalli, Mary Jane Irwin, Suman Datta, Vijaykrishnan Narayanan: Ultra Low Power Circuit Design Using Tunnel FETs. ISVLSI 2012: 153-158 |
| c219 | | Yong Cheol Peter Cho, Nandhini Chandramoorthy, Kevin M. Irick, Vijaykrishnan Narayanan: Multiresolution Gabor Feature Extraction for Real Time Applications. SiPS 2012: 55-60 |
| 2011 | ||
| j69 | | Vinay Saripalli, Guangyu Sun, Asit K. Mishra, Yuan Xie, Suman Datta, Vijaykrishnan Narayanan: Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(2): 109-119 (2011) |
| j68 | | Enrico Macii, Vijaykrishnan Narayanan, Kaushik Roy: Guest Editorial Advances in Design of Energy-Efficient Circuits and Systems (Second Issue). IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 205-207 (2011) |
| j67 | | Asit K. Mishra, Aditya Yanamandra, Reetuparna Das, Soumya Eachempati, Ravi R. Iyer, Narayanan Vijaykrishnan, Chita R. Das: RAFT: A router architecture with frequency tuning for on-chip networks. J. Parallel Distrib. Comput. 71(5): 625-640 (2011) |
| j66 | | Feng Wang, Yibo Chen, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan: Variation-Aware Task and Communication Mapping for MPSoC Architecture. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 295-307 (2011) |
| j65 | | Chi-Li Yu, Kevin M. Irick, Chaitali Chakrabarti, Vijaykrishnan Narayanan: Multidimensional DFT IP Generator for FPGA Platforms. IEEE Trans. on Circuits and Systems 58-I(4): 755-764 (2011) |
| j64 | | Chi-Li Yu, Jungsub Kim, Lanping Deng, Srinidhi Kestur, Vijaykrishnan Narayanan, Chaitali Chakrabarti: FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data. Signal Processing Systems 64(1): 109-122 (2011) |
| c218 | | Srinidhi Kestur, Kevin M. Irick, Sungho Park, Ahmed Al-Maashri, Vijaykrishnan Narayanan, Chaitali Chakrabarti: An algorithm-architecture co-design framework for gridding reconstruction using FPGAs. DAC 2011: 585-590 |
| c217 | | Vinay Saripalli, Asit K. Mishra, Suman Datta, Vijaykrishnan Narayanan: An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores. DAC 2011: 729-734 |
| c216 | | Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan: Automated mapping for reconfigurable single-electron transistor arrays. DAC 2011: 878-883 |
| c215 | | Srinidhi Kestur, Dharav Dantara, Vijaykrishnan Narayanan: SHARC: A streaming model for FPGA accelerators and its application to Saliency. DATE 2011: 1237-1242 |
| c214 | | Sungmin Bae, Yong Cheol Peter Cho, Sungho Park, Kevin M. Irick, Yongseok Jin, Vijaykrishnan Narayanan: An FPGA Implementation of Information Theoretic Visual-Saliency System and Its Optimization. FCCM 2011: 41-48 |
| c213 | | Srinidhi Kestur, Dharav Dantara, Vijaykrishnan Narayanan: A streaming FPGA implementation of a steerable filter for real-time applications (abstract only). FPGA 2011: 281 |
| c212 | | Yong Cheol Peter Cho, Sungmin Bae, Yongseok Jin, Kevin M. Irick, Vijaykrishnan Narayanan: Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA. FPL 2011: 311-316 |
| c211 | | Vijaykrishnan Narayanan, Vinay Saripalli, Karthik Swaminathan, Ravindhiran Mukundrajan, Guangyu Sun, Yuan Xie, Suman Datta: Enabling architectural innovations using non-volatile memory. ACM Great Lakes Symposium on VLSI 2011: 439-444 |
| c210 | | Michael DeBole, Ahmed Al-Maashri, Matthew Cotter, Chi-Li Yu, Chaitali Chakrabarti, Vijaykrishnan Narayanan: A framework for accelerating neuromorphic-vision algorithms on FPGAs. ICCAD 2011: 810-813 |
| c209 | | Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das: Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs. ISCA 2011: 69-80 |
| c208 | | Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das: A case for heterogeneous on-chip interconnects for CMPs. ISCA 2011: 389-400 |
| c207 | | Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta: Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores. ISLPED 2011: 247-252 |
| c206 | | Han-Wei Chen, Suresh Srinivasan, Yuan Xie, Vijaykrishnan Narayanan: Impact of Circuit Degradation on FPGA Design Security. ISVLSI 2011: 230-235 |
| c205 | | Karthik Swaminathan, Ravindhiran Mukundrajan, Niranjan Soundararajan, Vijaykrishnan Narayanan: Towards Resilient Micro-architectures: Datapath Reliability Enhancement Using STT-MRAM. ISVLSI 2011: 236-241 |
| c204 | | Ahmed Al-Maashri, Michael DeBole, Chi-Li Yu, Vijaykrishnan Narayanan, Chaitali Chakrabarti: A hardware architecture for accelerating neuromorphic vision algorithms. SiPS 2011: 355-360 |
| 2010 | ||
| b1 | | Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das: Network-on-Chip Architectures - A Holistic Design Exploration. Lecture Notes in Electrical Engineering 45, Springer 2010, isbn 978-90-481-3030-6, pp. 1-209 |
| j63 | | Vinay Saripalli, Lu Liu, Suman Datta, Vijaykrishnan Narayanan: Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits. J. Low Power Electronics 6(3): 415-428 (2010) |
| j62 | | Chrysostomos Nicopoulos, Suresh Srinivasan, Aditya Yanamandra, Dongkook Park, Vijaykrishnan Narayanan, Chita R. Das, Mary Jane Irwin: On the Effects of Process Variation in Network-on-Chip Architectures. IEEE Trans. Dependable Sec. Comput. 7(3): 240-254 (2010) |
| j61 | | Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Total Power Optimization for Combinational Logic Using Genetic Algorithms. Signal Processing Systems 58(2): 145-160 (2010) |
| c203 | | J. Singh, Krishnan Ramakrishnan, S. Mookerjea, Suman Datta, Narayanan Vijaykrishnan, D. K. Pradhan: A novel si-tunnel FET based SRAM design for ultra low-power 0.3V VDD applications. ASP-DAC 2010: 181-186 |
| c202 | | Aditya Yanamandra, Soumya Eachempati, Niranjan Soundararajan, Vijaykrishnan Narayanan, Mary Jane Irwin, Ramakrishnan Krishnan: Optimizing power and performance for reliable on-chip networks. ASP-DAC 2010: 431-436 |
| c201 | | Aditi Rathi, Michael DeBole, Weina Ge, Robert T. Collins, Narayanan Vijaykrishnan: A GPU based implementation of Center-Surround Distribution Distance for feature extraction and matching. DATE 2010: 172-177 |
| c200 | | Andrew J. Ricketts, J. Singh, Krishnan Ramakrishnan, Narayanan Vijaykrishnan, D. K. Pradhan: Investigating the impact of NBTI on different power saving cache strategies. DATE 2010: 592-597 |
| c199 |  | Vijaykrishnan Narayanan, Ahmed Al-Maashri, Kevin M. Irick, Michael DeBole, Sungho Park: AutoFLEX: A Framework for Image Processing Applications on Multiple-FPGA Systems. ERSA 2010: 59-66 |
| c198 | | Srinidhi Kestur, Sungho Park, Kevin M. Irick, Vijaykrishnan Narayanan: Accelerating the Nonuniform Fast Fourier Transform Using FPGAs. FCCM 2010: 19-26 |
| c197 | | Sungmin Bae, Narayanan Vijaykrishnan: Thermal Gradient Aware Clock Skew Scheduling for FPGAs. FPL 2010: 101-106 |
| c196 | | Chi-Li Yu, Chaitali Chakrabarti, Sungho Park, Vijaykrishnan Narayanan: Bandwidth-intensive FPGA architecture for multi-dimensional DFT. ICASSP 2010: 1486-1489 |
| c195 | | Vikram Sampath Kumar, Kevin M. Irick, Ahmed Al-Maashri, Narayanan Vijaykrishnan: A Scalable Bandwidth Aware Architecture for Connected Component Labeling. ISVLSI 2010: 116-121 |
| c194 | | Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta: Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors. VLSI Design 2010: 399-404 |
| 2009 | ||
| j60 | | Soumya Eachempati, Narayanan Vijaykrishnan, Arthur Nieuwoudt, Yehia Massoud: Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect. IET Circuits, Devices & Systems 3(2): 64-75 (2009) |
| j59 | | Richard R. Brooks, P. Y. Govindaraju, Matthew Pirretti, Narayanan Vijaykrishnan, Mahmut T. Kandemir: Clone Detection in Sensor Networks with Ad Hoc and Grid Topologies. IJDSN 5(3): 209-223 (2009) |
| j58 | | Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan: New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components. International Journal of Parallel Programming 37(4): 417-431 (2009) |
| j57 | | Madhu Mutyam, Feng Wang, Krishnan Ramakrishnan, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin: Process-Variation-Aware Adaptive Cache Architecture and Management. IEEE Trans. Computers 58(7): 865-877 (2009) |
| j56 | | Jungsub Kim, Lanping Deng, Prasanth Mangalagiri, Kevin M. Irick, Kanwaldeep Sobti, Mahmut T. Kandemir, Vijaykrishnan Narayanan, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun: An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization. IEEE Trans. Computers 58(12): 1654-1667 (2009) |
| j55 | | Tamer Ragheb, Andrew J. Ricketts, Mosin Mondal, Sami Kirolos, Greg M. Link, Vijaykrishnan Narayanan, Yehia Massoud: Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers. IEEE Trans. on Circuits and Systems 56-I(2): 374-383 (2009) |
| j54 | | Rajaraman Ramanarayanan, Vijay Degalahal, Krishnan Ramakrishnan, Jungsub Kim, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Kenan Unlu: Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits. IEEE Trans. Dependable Sec. Comput. 6(3): 202-216 (2009) |
| j53 | | Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Compiler-assisted soft error detection under performance and energy constraints in embedded systems. ACM Trans. Embedded Comput. Syst. 8(4) (2009) |
| c193 | | Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan: A framework for estimating NBTI degradation of microarchitectural components. ASP-DAC 2009: 455-460 |
| c192 | | Srinath Sridharan, Michael DeBole, Guangyu Sun, Yuan Xie, Vijaykrishnan Narayanan: A criticality-driven microarchitectural three dimensional (3D) floorplanner. ASP-DAC 2009: 763-768 |
| c191 | | Sungmin Bae, Prasanth Mangalagiri, Narayanan Vijaykrishnan: Exploiting clock skew scheduling for FPGA. DATE 2009: 1524-1529 |
| c190 | | Aditya Yanamandra, Mary Jane Irwin, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Sri Hari Krishna Narayanan: In-Network Caching for Chip Multiprocessors. HiPEAC 2009: 373-388 |
| c189 | | Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das: Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. HPCA 2009: 175-186 |
| c188 | | Suman Datta, Vijaykrishnan Narayanan: Green transistors to green architectures. ISLPED 2009: 429-430 |
| c187 | | Prasanth Mangalagiri, Vijaykrishnan Narayanan: Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs. ISVLSI 2009: 61-66 |
| c186 | | Sungmin Bae, Krishnan Ramakrishnan, Narayanan Vijaykrishnan: A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications. ISVLSI 2009: 193-198 |
| c185 | | Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer, Narayanan Vijaykrishnan, Chita R. Das: A case for dynamic frequency tuning in on-chip networks. MICRO 2009: 292-303 |
| c184 | | Padmaraj Singh, David L. Landis, Vijaykrishnan Narayanan: Test Generation for Precise Interrupts on Out-of-Order Microprocessors. MTV 2009: 79-82 |
| c183 | | Vinay Saripalli, Vijaykrishnan Narayanan, Suman Datta: Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors. NanoNet 2009: 200-209 |
| c182 | | Jungsub Kim, Chi-Li Yu, Lanping Deng, Srinidhi Kestur, Vijaykrishnan Narayanan, Chaitali Chakrabarti: FPGA architecture for 2D Discrete Fourier Transform based on 2D decomposition for large-sized data. SiPS 2009: 121-126 |
| c181 | | Jörg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran, Roshan G. Ragel: Security and Dependability of Embedded Systems: A Computer Architects' Perspective. VLSI Design 2009: 30-32 |
| 2008 | ||
| j52 | | Suresh Srinivasan, Lin Li, Martino Ruggiero, Federico Angiolini, Narayanan Vijaykrishnan, Luca Benini: Exploring architectural solutions for energy optimisations in bus-based system-on-chip. IET Computers & Digital Techniques 2(5): 347-354 (2008) |
| j51 | | |
| j50 | | Suresh Srinivasan, Krishnan Ramakrishnan, Prasanth Mangalagiri, Yuan Xie, Vijaykrishnan Narayanan, Mary Jane Irwin, Karthik Sarpatwari: Toward Increasing FPGA Lifetime. IEEE Trans. Dependable Sec. Comput. 5(2): 115-127 (2008) |
| j49 | | Yuh-Fang Tsai, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Design Space Exploration for 3-D Cache. IEEE Trans. VLSI Syst. 16(4): 444-455 (2008) |
| j48 | | Shengqi Yang, Wenping Wang, Tiehan Lv, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie: Case Study of Reliability-Aware and Low-Power Design. IEEE Trans. VLSI Syst. 16(7): 861-873 (2008) |
| j47 | | Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arifur Rahman: Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues. IEEE Trans. VLSI Syst. 16(7): 882-893 (2008) |
| c180 | | David Atienza, Giovanni De Micheli, Luca Benini, José L. Ayala, Pablo Garcia Del Valle, Michael DeBole, Vijaykrishnan Narayanan: Reliability-aware design for nanometer-scale devices. ASP-DAC 2008: 549-554 |
| c179 | | Niranjan Soundararajan, Aditya Yanamandra, Chrysostomos Nicopoulos, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin: Analysis and solutions to issue queue process variation. DSN 2008: 11-21 |
| c178 | | Kevin M. Irick, Michael DeBole, Vijaykrishnan Narayanan, Aman Gayasen: A Hardware Efficient Support Vector Machine Architecture for FPGA. FCCM 2008: 304-305 |
| c177 | | Prasanth Mangalagiri, Karthik Sarpatwari, Aditya Yanamandra, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Osama Awadel Karim: A low-power phase change memory based hybrid cache architecture. ACM Great Lakes Symposium on VLSI 2008: 395-398 |
| c176 | | Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Mazin S. Yousif, Chita R. Das: Performance and power optimization through data compression in Network-on-Chip architectures. HPCA 2008: 215-225 |
| c175 | | Prasanth Mangalagiri, Sungmin Bae, Krishnan Ramakrishnan, Yuan Xie, Vijaykrishnan Narayanan: Thermal-aware reliability analysis for platform FPGAs. ICCAD 2008: 722-727 |
| c174 | | Krishnan Ramakrishnan, Xiaoxia Wu, Narayanan Vijaykrishnan, Yuan Xie: Comparative analysis of NBTI effects on low power and high performance flip-flops. ICCD 2008: 200-205 |
| c173 | | Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das: MIRA: A Multi-layered On-Chip Interconnect Router Architecture. ISCA 2008: 251-261 |
| c172 | | Niranjan Soundararajan, Narayanan Vijaykrishnan, Anand Sivasubramaniam: Impact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architectures. ISLPED 2008: 351-356 |
| c171 | | Krishnan Ramakrishnan, R. Rajaraman, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin, Kenan Unlu: Hierarchical Soft Error Estimation Tool (HSEET). ISQED 2008: 680-683 |
| c170 | | Lanping Deng, Chi-Li Yu, Chaitali Chakrabarti, Jungsub Kim, Vijaykrishnan Narayanan: Efficient image reconstruction using partial 2D Fourier transform. SiPS 2008: 49-54 |
| e4 | | Vijaykrishnan Narayanan, Zhiyuan Yan, Enrico Macii, Sanjukta Bhanja (Eds.): Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008. ACM 2008, isbn 978-1-59593-999-9 |
| e3 | | Vijaykrishnan Narayanan, C. P. Ravikumar, Jörg Henkel, Ali Keshavarzi, Vojin G. Oklobdzija, Barry M. Pangrle (Eds.): Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008. ACM 2008, isbn 978-1-60558-109-5 |
| 2007 | ||
| j46 | | Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir: Optimising power efficiency in trace cache fetch unit. IET Computers & Digital Techniques 1(4): 334-348 (2007) |
| j45 | | Feng Wang, Michael DeBole, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: On-chip bus thermal analysis and optimisation. IET Computers & Digital Techniques 1(5): 590-599 (2007) |
| j44 | | Aman Gayasen, Suresh Srinivasan, Narayanan Vijaykrishnan, Mahmut T. Kandemir: Design of power-aware FPGA fabrics. IJES 3(1/2): 52-64 (2007) |
| j43 | | Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin: Reducing non-deterministic loads in low-power caches via early cache set resolution. Microprocessors and Microsystems 31(5): 293-301 (2007) |
| j42 | | Tao Li, Lizy Kurian John, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Juan Rubio: OS-Aware Branch Prediction: Improving Microprocessor Control Flow Prediction for Operating Systems. IEEE Trans. Computers 56(1): 2-17 (2007) |
| j41 | | Richard R. Brooks, P. Y. Govindaraju, Matthew Pirretti, Narayanan Vijaykrishnan, Mahmut T. Kandemir: On the Detection of Clones in Sensor Networks Using Random Key Predistribution. IEEE Transactions on Systems, Man, and Cybernetics, Part C 37(6): 1246-1258 (2007) |
| j40 | | Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Reliability-aware Co-synthesis for Embedded Systems. VLSI Signal Processing 49(1): 87-99 (2007) |
| c169 | | Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen, Narayanan Vijaykrishnan, Yehia Massoud: Assessing carbon nanotube bundle interconnect for future FPGA architectures. DATE 2007: 307-312 |
| c168 | | Madhu Mutyam, Narayanan Vijaykrishnan: Working with process variation aware caches. DATE 2007: 1152-1157 |
| c167 | | Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud: Thermally robust clocking schemes for 3D integrated circuits. DATE 2007: 1206-1211 |
| c166 | | Jungsub Kim, Prasanth Mangalagiri, Kevin M. Irick, Mahmut T. Kandemir, Vijaykrishnan Narayanan, Kanwaldeep Sobti, Lanping Deng, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun: TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms. FPL 2007: 68-73 |
| c165 | | Kevin M. Irick, Michael DeBole, Vijaykrishnan Narayanan, Rajeev Sharma, Hankyu Moon, Satish Mummareddy: A Unified Streaming Architecture for Real Time Face Detection and Gender Classification. FPL 2007: 267-272 |
| c164 | | Dongkook Park, Reetuparna Das, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Ravishankar R. Iyer, Chita R. Das: Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects. Hot Interconnects 2007: 15-20 |
| c163 | | Feng Wang, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan: Variation-aware task allocation and scheduling for MPSoC. ICCAD 2007: 598-603 |
| c162 | | Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan: FPGA routing architecture analysis under variations. ICCD 2007: 152-157 |
| c161 | | Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das: A novel dimensionally-decomposed router for on-chip communication in 3D architectures. ISCA 2007: 138-149 |
| c160 | | Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud: Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers. ISQED 2007: 67-72 |
| c159 | | Amol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Variation Analysis of CAM Cells. ISQED 2007: 333-338 |
| c158 | | Krishnan Ramakrishnan, R. Rajaraman, Sivaprakasam Suresh, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Variation Impact on SER of Combinational Circuits. ISQED 2007: 911-916 |
| c157 | | Andrew J. Ricketts, Madhu Mutyam, Narayanan Vijaykrishnan, Mary Jane Irwin: Investigating Simple Low Latency Reliable Multiported Register Files. ISVLSI 2007: 375-382 |
| c156 | | Soumya Eachempati, Narayanan Vijaykrishnan, Arthur Nieuwoudt, Yehia Massoud: Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures. ISVLSI 2007: 516-517 |
| c155 | | Kanwaldeep Sobti, Lanping Deng, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun, Jungsub Kim, Prasanth Mangalagiri, Kevin M. Irick, Mahmut T. Kandemir, Vijaykrishnan Narayanan: Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations. SiPS 2007: 463-468 |
| c154 | | Balaji Vaidyanathan, Wei-Lun Hung, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Architecting Microprocessor Components in 3D Design Space. VLSI Design 2007: 103-108 |
| c153 | | Krishnan Ramakrishnan, Sivaprakasam Suresh, Narayanan Vijaykrishnan, Mary Jane Irwin: Impact of NBTI on FPGAs. VLSI Design 2007: 717-722 |
| e2 | | Diana Marculescu, Anand Raghunathan, Ali Keshavarzi, Vijaykrishnan Narayanan (Eds.): Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007. ACM 2007, isbn 978-1-59593-709-4 |
| i3 | | Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Thermal-Aware Task Allocation and Scheduling for Embedded Systems. CoRR abs/0710.4660 (2007) |
| i2 | | Yuh-Fang Tsai, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin: Leakage-Aware Interconnect for On-Chip Network. CoRR abs/0710.4731 (2007) |
| i1 | | Greg M. Link, Narayanan Vijaykrishnan: Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip. CoRR abs/0710.4764 (2007) |
| 2006 | ||
| j39 | | Narayanan Vijaykrishnan, Yuan Xie: Reliability Concerns in Embedded System Designs. IEEE Computer 39(1): 118-120 (2006) |
| j38 | | Matthew Pirretti, Sencun Zhu, Narayanan Vijaykrishnan, Patrick McDaniel, Mahmut T. Kandemir, Richard R. Brooks: The Sleep Deprivation Attack in Sensor Networks: Analysis and Methods of Defense. IJDSN 2(3): 267-287 (2006) |
| j37 | | Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf: An efficient architecture for motion estimation and compensation in the transform domain. IEEE Trans. Circuits Syst. Video Techn. 16(2): 191-201 (2006) |
| j36 | | Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin: Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties. IEEE Trans. Circuits Syst. Video Techn. 16(5): 655-662 (2006) |
| j35 | | Wei Zhang, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Reducing dynamic and leakage energy in VLIW architectures. ACM Trans. Embedded Comput. Syst. 5(1): 1-28 (2006) |
| j34 | | Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Rajarathnam Chandramouli: Block-based frequency scalable technique for efficient hierarchical coding. IEEE Transactions on Signal Processing 54(7): 2559-2566 (2006) |
| c152 | | Balaji Vaidyanathan, Suresh Srinivasan, Yuan Xie, Narayanan Vijaykrishnan, Rong Luo: Leakage Optimized DECAP Design for FPGAs. APCCAS 2006: 960-963 |
| c151 | | Guilin Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Object duplication for improving reliability. ASP-DAC 2006: 140-145 |
| c150 | | Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan, Karthik Sarpatwari: FLAW: FPGA lifetime awareness. DAC 2006: 630-635 |
| c149 | | Andrew J. Ricketts, Kevin M. Irick, Narayanan Vijaykrishnan, Mary Jane Irwin: Priority scheduling in digital microfluidics-based biochips. DATE 2006: 329-334 |
| c148 | | Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: On-chip bus thermal analysis and optimization. DATE 2006: 850-855 |
| c147 | | Dongkook Park, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Chita R. Das: Exploring Fault-Tolerant Network-on-Chip Architectures. DSN 2006: 93-104 |
| c146 | | Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arif Rahman: Switch Box Architectures for Three-Dimensional FPGAs. FCCM 2006: 335-336 |
| c145 | | Priya Sundararajan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan: Thermal characterization and optimization in platform FPGAs. ICCAD 2006: 443-447 |
| c144 | | Feihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir: Design and Management of 3D Chip Multiprocessors Using Network-in-Memory. ISCA 2006: 130-141 |
| c143 | | Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Interconnect and Thermal-aware Floorplanning for 3D Microprocessors. ISQED 2006: 98-104 |
| c142 | | |
| c141 | | Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada: Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. ISQED 2006: 775-780 |
| c140 | | Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie: Reliability-Aware SOC Voltage Islands Partition and Floorplan. ISVLSI 2006: 343-348 |
| c139 | | Madhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie: Delay and Energy Efficient Data Transmission for On-Chip Buses. ISVLSI 2006: 355-360 |
| c138 | | Suresh Srinivasan, Narayanan Vijaykrishnan: Variation Aware Placement for FPGAs. ISVLSI 2006: 422-423 |
| c137 | | Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin: A Parallel Architecture for Hardware Face Detection. ISVLSI 2006: 452-453 |
| c136 | | Madhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Compiler-directed thermal management for VLIW functional units. LCTES 2006: 163-172 |
| c135 | | Chrysostomos Nicopoulos, Dongkook Park, Jongman Kim, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das: ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers. MICRO 2006: 333-346 |
| c134 | | Priya Sundararajan, Sridhar Krishnamurthy, Narayanan Vijaykrishnan, Kamal Chaudhary, Rajeev Jayaraman: Performance Improvements through Timing Driven Reconfiguration of Black-Boxes in Platform FPGAs. SoCC 2006: 105-106 |
| c133 | | Suresh Srinivasan, Raghavan Ramadoss, Narayanan Vijaykrishnan: Process Variation Aware Parallelization Strategies for MPSoCs. SoCC 2006: 179-182 |
| c132 | | R. Rajaraman, Jungsub Kim, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: SEAT-LA: A Soft Error Analysis Tool for Combinational Logic. VLSI Design 2006: 499-502 |
| c131 | | Thomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie, Chita R. Das, Vijay Degalahal: A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks. VLSI Design 2006: 657-664 |
| e1 | | Gang Qu, Yehea I. Ismail, Narayanan Vijaykrishnan, Hai Zhou (Eds.): Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006. ACM 2006, isbn 1-59593-347-6 |
| 2005 | ||
| j33 | | Theocharis Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin: Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip. Advances in Computers 63: 36-92 (2005) |
| j32 | | Srinivasan Murali, Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin, Luca Benini, Giovanni De Micheli: Analysis of Error Recovery Schemes for Networks on Chips. IEEE Design & Test of Computers 22(5): 434-442 (2005) |
| j31 | | Eric J. Swankoski, Narayanan Vijaykrishnan, Richard R. Brooks, Mahmut T. Kandemir, Mary Jane Irwin: Symmetric encryption in reconfigurable and custom hardware. IJES 1(3/4): 205-217 (2005) |
| j30 | | Emanuele Lattanzi, Aman Gayasen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Luca Benini, Alessandro Bogliolo: Improving Java performance using dynamic method migration on FPGAs. IJES 1(3/4): 228-236 (2005) |
| j29 | | |
| j28 | | Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: An integer linear programming-based tool for wireless sensor networks. J. Parallel Distrib. Comput. 65(3): 247-260 (2005) |
| j27 | | Eun Jung Kim, Greg M. Link, Ki Hwan Yum, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Chita R. Das: A Holistic Approach to Designing Energy-Efficient Cluster Interconnects. IEEE Trans. Computers 54(6): 660-671 (2005) |
| j26 | | Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan: Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations. IEEE Trans. Computers 54(6): 714-726 (2005) |
| j25 | | Ismail Kadayif, Mahmut T. Kandemir, Guilin Chen, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam: Compiler-directed high-level energy estimation and optimization. ACM Trans. Embedded Comput. Syst. 4(4): 819-850 (2005) |
| j24 | | Jie S. Hu, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Analyzing data reuse for cache reconfiguration. ACM Trans. Embedded Comput. Syst. 4(4): 851-876 (2005) |
| j23 | | Vijay Degalahal, Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Soft errors issues in low-power caches. IEEE Trans. VLSI Syst. 13(10): 1157-1166 (2005) |
| c130 | | Jongman Kim, Dongkook Park, Chrysostomos Nicopoulos, Narayanan Vijaykrishnan, Chita R. Das: Design and analysis of an NoC architecture from performance, reliability and energy perspective. ANCS 2005: 173-182 |
| c129 | | Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Designing reliable circuit in the presence of soft errors. ASP-DAC 2005: 1 |
| c128 | | Shengqi Yang, Wayne Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie: Low-leakage robust SRAM cell design for sub-100nm technologies. ASP-DAC 2005: 539-544 |
| c127 | | Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan: Leakage control in FPGA routing fabric. ASP-DAC 2005: 661-664 |
| c126 | | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan: Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs. ASP-DAC 2005: 1200-1203 |
| c125 | | Nagu R. Dhanwada, Ing-Chao Lin, Vijaykrishnan Narayanan: A power estimation methodology for systemC transaction level models. CODES+ISSS 2005: 142-147 |
| c124 | | Jongman Kim, Dongkook Park, Theo Theocharides, Narayanan Vijaykrishnan, Chita R. Das: A low latency router supporting adaptivity for on-chip interconnects. DAC 2005: 559-564 |
| c123 | | Aman Gayasen, Narayanan Vijaykrishnan, Mary Jane Irwin: Exploring technology alternatives for nano-scale FPGA interconnects. DAC 2005: 921-926 |
| c122 | | Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Dimitrios N. Serpanos, Yuan Xie: Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach. DATE 2005: 64-69 |
| c121 | | Suresh Srinivasan, Lin Li, Narayanan Vijaykrishnan: Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures. DATE 2005: 218-223 |
| c120 | | Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Leakage-Aware Interconnect for On-Chip Network. DATE 2005: 230-231 |
| c119 | | Greg M. Link, Narayanan Vijaykrishnan: Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip. DATE 2005: 648-649 |
| c118 | | Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Thermal-Aware Task Allocation and Scheduling for Embedded Systems. DATE 2005: 898-899 |
| c117 | | Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Compiler-Directed Instruction Duplication for Soft Error Detection. DATE 2005: 1056-1057 |
| c116 | | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan: Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only). FPGA 2005: 265 |
| c115 | | Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Three-Dimensional Cache Design Exploration Using 3DCacti. ICCD 2005: 519-524 |
| c114 | | Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwada, John Conner: Temperature-Aware Voltage Islands Architecting in System-on-Chip Design. ICCD 2005: 689-696 |
| c113 | | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan: Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs. IPDPS 2005 |
| c112 | | Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Charles Addo-Quaye, Theo Theocharides, Mary Jane Irwin: Thermal-Aware Floorplanning Using Genetic Algorithms. ISQED 2005: 634-639 |
| c111 | | Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin: High Performance Array Processor for Video Decoding. ISVLSI 2005: 28-33 |
| c110 | | Hendra Saputra, Ozcan Ozturk, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Richard R. Brooks: A Data-Driven Approach for Embedded Security. ISVLSI 2005: 104-109 |
| c109 | | |
| c108 | | Suresh Srinivasan, Federico Angiolini, Martino Ruggiero, Luca Benini, Narayanan Vijaykrishnan: Simultaneous memory and bus partitioning for SoC architectures. SoCC 2005: 125-128 |
| c107 | | Theo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin: Implementing LDPC Decoding on Network-on-Chip. VLSI Design 2005: 134-137 |
| c106 | | Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie, Wenping Wang: Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits. VLSI Design 2005: 165-170 |
| c105 | | Kevin M. Irick, Wei Xu, Narayanan Vijaykrishnan, Mary Jane Irwin: A Nanosensor Array-Based VLSI Gas Discriminator. VLSI Design 2005: 241-246 |
| c104 | | Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty. VLSI Design 2005: 374-379 |
| c103 | | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan: Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. VLSI Design 2005: 736-741 |
| 2004 | ||
| j22 | | Soontae Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Optimizing Leakage Energy Consumption in Cache Bitlines. Design Autom. for Emb. Sys. 9(1): 5-18 (2004) |
| j21 | | Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Reducing instruction cache energy consumption using a compiler-based strategy. TACO 1(1): 3-33 (2004) |
| j20 | | Mahmut T. Kandemir, J. Ramanujam, Mary Jane Irwin, Narayanan Vijaykrishnan, Ismail Kadayif, Amisha Parikh: A compiler-based approach for dynamically managing scratch-pad memories in embedded systems. IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 243-260 (2004) |
| j19 | | Guangyu Chen, Byung-Tae Kang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Rajarathnam Chandramouli: Studying Energy Trade Offs in Offloading Computation/Compilation in Java-Enabled Mobile Devices. IEEE Trans. Parallel Distrib. Syst. 15(9): 795-809 (2004) |
| j18 | | Christian Piguet, Narayanan Vijaykrishnan: Guest Editorial. IEEE Trans. VLSI Syst. 12(2): 129-130 (2004) |
| j17 | | Christian Piguet, Narayanan Vijaykrishnan: Guest Editorial. IEEE Trans. VLSI Syst. 12(3): 233-234 (2004) |
| j16 | | Yuh-Fang Tsai, D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin: Characterization and modeling of run-time techniques for leakage power reduction. IEEE Trans. VLSI Syst. 12(11): 1221-1233 (2004) |
| j15 | | Amisha Parikh, Soontae Kim, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Instruction Scheduling for Low Power. VLSI Signal Processing 37(1): 129-149 (2004) |
| j14 | | J. Juran, Ali R. Hurson, Narayanan Vijaykrishnan, Soontae Kim: Data Organization and Retrieval on Parallel Air Channels: Performance and Energy Issues. Wireless Networks 10(2): 183-195 (2004) |
| c102 | | Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Reliability-Aware Co-Synthesis for Embedded Systems. ASAP 2004: 41-50 |
| c101 | | Guilin Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin: Analyzing heap error behavior in embedded JVM environments. CODES+ISSS 2004: 230-235 |
| c100 | | Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: A Crosstalk Aware Interconnect with Variable Cycle Transmission. DATE 2004: 102-107 |
| c99 | | Jie S. Hu, Narayanan Vijaykrishnan, Soontae Kim, Mahmut T. Kandemir, Mary Jane Irwin: Scheduling Reusable Instructions for Power Reduction. DATE 2004: 148-155 |
| c98 | | Aman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan: Reducing leakage energy in FPGAs using region-constrained placement. FPGA 2004: 51-58 |
| c97 | | Aman Gayasen, K. Lee, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan: A Dual-VDD Low Power FPGA Architecture. FPL 2004: 145-157 |
| c96 | | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Vijaykrishnan Narayanan: A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs. FPT 2004: 121-128 |
| c95 | | Wei Xu, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Design of a nanosensor array architecture. ACM Great Lakes Symposium on VLSI 2004: 298-303 |
| c94 | | Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin: Exploring Wakeup-Free Instruction Scheduling. HPCA 2004: 232-243 |
| c93 | | Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin: Improving soft-error tolerance of FPGA configuration bits. ICCAD 2004: 107-110 |
| c92 | | Frank Ghenassia, Narayanan Vijaykrishnan, Mary Jane Irwin: Analyzing software influences on substrate noise: an ADC perspective. ICCAD 2004: 916-922 |
| c91 | | Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharides, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture. ICCD 2004: 430-437 |
| c90 | | Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan: Search speed and power driven integrated software and hardware optimizations for motion estimation algorithms. ICME 2004: 707-710 |
| c89 | | Emanuele Lattanzi, Aman Gayasen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Luca Benini, Alessandro Bogliolo: Improving Java Performance Using Dynamic Method Migration on FPGAs. IPDPS 2004 |
| c88 | | Eric J. Swankoski, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: A Parallel Architecture for Secure FPGA Symmetric Encryption. IPDPS 2004 |
| c87 | | Lin Li, Vijay Degalahal, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Soft error and energy consumption interactions: a data cache perspective. ISLPED 2004: 132-137 |
| c86 | | Vijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: The Effect of Threshold Voltages on the Soft Error Rate. ISQED 2004: 503-508 |
| c85 | | Matthew Pirretti, Greg M. Link, Richard R. Brooks, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Fault Tolerant Algorithms for Network-On-Chip Interconnect. ISVLSI 2004: 46-51 |
| c84 | | Theo Theocharides, Greg M. Link, Eric J. Swankoski, Narayanan Vijaykrishnan, Mary Jane Irwin, Herman Schmit: Evaluating Alternative Implementations for LDPC Decoder Check Node Function. ISVLSI 2004: 77-82 |
| c83 | | Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Field level analysis for heap space optimization in embedded java environments. ISMM 2004: 131-142 |
| c82 | | Hendra Saputra, Guangyu Chen, Richard R. Brooks, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Code protection for resource-constrained embedded devices. LCTES 2004: 240-248 |
| c81 | | Byung-Tae Kang, Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides: Power-efficient implementation of turbo decoder in SDR system. SoCC 2004: 119-122 |
| c80 | | Theocharis Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin, Vamsi Srikantam: A generic reconfigurable neural network architecture as a network on chip. SoCC 2004: 191-194 |
| c79 | | Yuh-Fang Tsai, Ananth Hegde Ankadi, Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides: ChipPower: an architecture-level leakage simulator. SoCC 2004: 395-398 |
| c78 | | Theo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf: Embedded Hardware Face Detection. VLSI Design 2004: 133- |
| c77 | | M. DeRenzo, Mary Jane Irwin, Narayanan Vijaykrishnan: Designing Leakage Aware Multipliers. VLSI Design 2004: 654-657 |
| c76 | | Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf: An Architecture for Motion Estimation in the Transform Domain. VLSI Design 2004: 1077-1082 |
| 2003 | ||
| j13 | | Nam Sung Kim, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner, Jie S. Hu, Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan: Leakage Current: Moore's Law Meets Static Power. IEEE Computer 36(12): 68-75 (2003) |
| j12 | | Lin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam: Managing Leakage Energy in Cache Hierarchies. J. Instruction-Level Parallelism 5 (2003) |
| j11 | | Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye, David Duarte: Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework. IEEE Trans. Computers 52(1): 59-76 (2003) |
| j10 | | Soontae Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin: Partitioned instruction cache architecture for energy efficiency. ACM Trans. Embedded Comput. Syst. 2(2): 163-185 (2003) |
| c75 | | Ananth Hegde, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: VL-CDRAM: variable line sized cached DRAMs. CODES+ISSS 2003: 132-137 |
| c74 | | Guangyu Chen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Mario Wolczko: Tracking object life cycle for leakage energy optimization. CODES+ISSS 2003: 213-218 |
| c73 | | Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin: Implications of technology scaling on leakage reduction techniques. DAC 2003: 187-190 |
| c72 | | Hendra Saputra, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Richard R. Brooks, Soontae Kim, Wei Zhang: Masking the Energy Behavior of DES Encryption. DATE 2003: 10084-10089 |
| c71 | | Wei Zhang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Vivek De: Compiler Support for Reducing Leakage Energy Consumption. DATE 2003: 11146-11147 |
| c70 | | Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Ismail Kadayif: CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors. DSD 2003: 41-49 |
| c69 | | Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Adapative Error Protection for Energy Efficiency. ICCAD 2003: 2-7 |
| c68 | | Victor Delaluz, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin, Narayanan Vijaykrishnan: Reducing dTLB Energy Through Dynamic Resizing. ICCD 2003: 358-363 |
| c67 | | Amol Bhatkar, Rajarathnam Chandramouli, Narayanan Vijaykrishnan, Mary Jane Irwin: Computation and transmission energy modeling through profiling for MPEG4 video transmission. ICME 2003: 281-284 |
| c66 | | Sudhanva Gurumurthi, Ning An, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Energy and Performance Considerations in Work Partitioning for Mobile Spatial Queries. IPDPS 2003: 33 |
| c65 | | Guilin Chen, Byung-Tae Kang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Rajarathnam Chandramouli: Energy-Aware Compilation and Execution in Java-Enabled Mobile Devices. IPDPS 2003: 34 |
| c64 | | Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Erik Brockmeyer, Francky Catthoor, Mary Jane Irwin: Estimating influence of data layout optimizations on SDRAM energy consumption. ISLPED 2003: 40-43 |
| c63 | | Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin, Lizy Kurian John: On load latency in low-power caches. ISLPED 2003: 258-261 |
| c62 | | Jie S. Hu, A. Nadgir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir: Exploiting program hotspots and code sequentiality for instruction cache leakage management. ISLPED 2003: 402-407 |
| c61 | | Eun Jung Kim, Ki Hwan Yum, Greg M. Link, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Mazin S. Yousif, Chita R. Das: Energy optimization techniques in cluster interconnects. ISLPED 2003: 459-464 |
| c60 | | Sudhanva Gurumurthi, Jianyong Zhang, Anand Sivasubramaniam, Mahmut T. Kandemir, Hubertus Franke, Narayanan Vijaykrishnan, Mary Jane Irwin: Interplay of energy and performance for disk arrays running transaction processing workloads. ISPASS 2003: 123-132 |
| c59 | | Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir: Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch. ISVLSI 2003: 127-132 |
| c58 | | Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Adapting instruction level parallelism for optimizing leakage in VLIW architectures. LCTES 2003: 275-283 |
| c57 | | Herman Schmit, Thomas Kroll, Max Khusid, Ivan S. Kourtev, Narayanan Vijaykrishnan, David L. Landis: The Sandbox Design Experience Course. MSE 2003: 39-40 |
| c56 | | Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Bernd Mathiske, Mario Wolczko: Heap compression for memory-constrained Java environments. OOPSLA 2003: 282-301 |
| c55 | | |
| c54 | | Vijay Degalahal, Narayanan Vijaykrishnan, Mary Jane Irwin: Analyzing Soft Errors in Leakage Optimized SRAM Design. VLSI Design 2003: 227-233 |
| 2002 | ||
| j9 | | Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf: Using Memory Compression for Energy Reduction in an Embedded Java System. Journal of Circuits, Systems, and Computers 11(5): 537-556 (2002) |
| j8 | | Guangyu Chen, R. Shetty, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mario Wolczko: Tuning garbage collection for reducing memory system energy in an embedded java environment. ACM Trans. Embedded Comput. Syst. 1(1): 27-55 (2002) |
| j7 | | D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin: A clock power model to evaluate impact of architectural and technology optimizations. IEEE Trans. VLSI Syst. 10(6): 844-855 (2002) |
| j6 | | Ning An, Sudhanva Gurumurthi, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Energy-performance trade-offs for spatial access methods on memory-resident data. VLDB J. 11(3): 179-197 (2002) |
| c53 | | Lin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam: Leakage Energy Management in Cache Hierarchies. IEEE PACT 2002: 131-140 |
| c52 | | Tao Li, Lizy Kurian John, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Juan Rubio: Understanding and improving operating system effects in control flow prediction. ASPLOS 2002: 68-80 |
| c51 | | Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf: Energy savings through compression in embedded Java environments. CODES 2002: 163-168 |
| c50 | | Victor Delaluz, Anand Sivasubramaniam, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Scheduler-based DRAM energy management. DAC 2002: 697-702 |
| c49 | | Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam: EAC: A Compiler Framework for High-Level Energy Estimation and Optimization. DATE 2002: 436-442 |
| c48 | | Jie S. Hu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Power-Efficient Trace Caches. DATE 2002: 1091 |
| c47 | | David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin: A Complete Phase-Locked Loop Power Consumption Model. DATE 2002: 1108 |
| c46 | | Guangyu Chen, R. Shetty, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mario Wolczko: Tuning Garbage Collection in an Embedded Java Environment. HPCA 2002: 92-103 |
| c45 | | Sudhanva Gurumurthi, Anand Sivasubramaniam, Mary Jane Irwin, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Tao Li, Lizy Kurian John: Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach. HPCA 2002: 141-150 |
| c44 | | Byung-Tae Kang, Vijaykrishnan Narayanan, Mary Jane Irwin, Rajarathnam Chandramouli: Power efficient adaptive M-QAM design using adaptive pipelined analog-to-digital converter. ICASSP 2002: 2705-2708 |
| c43 | | David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin, Hyun Suk Kim, G. McFarland: Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes. ICCD 2002: 382-387 |
| c42 | | Anand Sivasubramaniam, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Designing Energy-Efficient Software. IPDPS 2002 |
| c41 | | Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Hardware-Software Co-Adaptation for Data-Intensive Embedded Applications. ISVLSI 2002: 20-25 |
| c40 | | David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin: Impact of Technology Scaling in the Clock System Power. ISVLSI 2002: 59-64 |
| c39 | | Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mario Wolczko: Adaptive Garbage Collection for Battery-Operated Environments. Java Virtual Machine Research and Technology Symposium 2002: 1-12 |
| c38 | | Hendra Saputra, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Jie S. Hu, Chung-Hsing Hsu, Ulrich Kremer: Energy-conscious compilation based on voltage scaling. LCTES-SCOPES 2002: 2-11 |
| c37 | | Jie S. Hu, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Hendra Saputra, Wei Zhang: Compiler-directed cache polymorphism. LCTES-SCOPES 2002: 165-174 |
| c36 | | Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Compiler-directed instruction cache leakage optimization. MICRO 2002: 208-218 |
| c35 | | David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin: Evaluating Run-Time Techniques for Leakage Power Reduction. VLSI Design 2002: 31-38 |
| c34 | | Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam, Ibrahim Kolcu: Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories. VLSI Design 2002: 288- |
| 2001 | ||
| j5 | | Ramesh Radhakrishnan, Narayanan Vijaykrishnan, Lizy Kurian John, Anand Sivasubramaniam, Juan Rubio, Jyotsna Sabarinathan: Java Runtime Systems: Characterization and Architectural Implications. IEEE Trans. Computers 50(2): 131-146 (2001) |
| j4 | | Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin: Hardware and Software Techniques for Controlling DRAM Power Modes. IEEE Trans. Computers 50(11): 1154-1173 (2001) |
| j3 | | Benjamin Bishop, V. Lyuboslavsky, Narayanan Vijaykrishnan, Mary Jane Irwin: Design considerations for databus charge recovery. IEEE Trans. VLSI Syst. 9(1): 104-106 (2001) |
| j2 | | Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wu Ye: Influence of compiler optimizations on system power. IEEE Trans. VLSI Syst. 9(6): 801-804 (2001) |
| c33 | | Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Energy-efficient instruction cache using page-based placement. CASES 2001: 229-237 |
| c32 | | Mahmut T. Kandemir, J. Ramanujam, Mary Jane Irwin, Narayanan Vijaykrishnan, Ismail Kadayif, Amisha Parikh: Dynamic Management of Scratch-Pad Memory Space. DAC 2001: 690-695 |
| c31 | | Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin: DRAM Energy Management Using Software and Hardware Directed Power Mode Control. HPCA 2001: 159-169 |
| c30 | | Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: A Framework for Energy Estimation of VLIW Architecture. ICCD 2001: 40-45 |
| c29 | | Samarjeet Singh Tomar, Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Use of Local Memory for Efficient Java Execution. ICCD 2001: 468-476 |
| c28 | | R. Athavale, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Influence of Array Allocation Mechanisms on Memory System Energy. IPDPS 2001: 3 |
| c27 | | Soontae Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin, E. Geethanjali: Power-aware partitioned cache architectures. ISLPED 2001: 64-67 |
| c26 | | Narayanan Vijaykrishnan, Mahmut T. Kandemir, Soontae Kim, Samarjeet Singh Tomar, Anand Sivasubramaniam, Mary Jane Irwin: Energy Behavior of Java Applications from the Memory Perspective. Java Virtual Machine Research and Technology Symposium 2001: 207-220 |
| c25 | | Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, J. Ramanujam: Morphable Cache Architectures: Potential Benefits. LCTES/OM 2001: 128-137 |
| c24 | | Wei Zhang, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai: Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. MICRO 2001: 102-113 |
| c23 | | Pradeep K. Khosla, Herman Schmit, Mary Jane Irwin, Narayanan Vijaykrishnan, Tom Cain, Steven P. Levitan, Dave Landis: SoC Design Skills: Collaboration Builds a Stronger SoC Design Team. MSE 2001: 42-43 |
| c22 | | Ismail Kadayif, T. Chinoda, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam: vEC: virtual energy counters. PASTE 2001: 28-31 |
| c21 | | Ning An, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Sudhanva Gurumurthi: Analyzing energy behavior of spatial access methods for memory-resident data. VLDB 2001: 411-420 |
| c20 | | David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir: Formulation and Validation of an Energy Dissipation Model for the Clock Generation Circuitry and Distribution Networks. VLSI Design 2001: 248-253 |
| 2000 | ||
| c19 | | Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Energy-oriented compiler optimizations for partitioned memory architectures. CASES 2000: 138-147 |
| c18 | | Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wu Ye: Influence of compiler optimizations on system power. DAC 2000: 304-307 |
| c17 | | Wu Ye, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: The design and use of simplepower: a cycle-accurate energy estimation tool. DAC 2000: 340-345 |
| c16 | | Jeyran Hezavei, Narayanan Vijaykrishnan, Mary Jane Irwin: A comparative study of power efficient SRAM designs. ACM Great Lakes Symposium on VLSI 2000: 117-122 |
| c15 | | Amisha Parikh, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Energy-Aware Instruction Scheduling. HiPC 2000: 335-344 |
| c14 | | J. Juran, Ali R. Hurson, Narayanan Vijaykrishnan, S. Boonsiriwattanakul: Data Organization and Retrieval on Parallel Air Channels. HiPC 2000: 501-510 |
| c13 | | Ramesh Radhakrishnan, Narayanan Vijaykrishnan, Lizy Kurian John, Anand Sivasubramaniam: Architectural Issues in Java Runtime Systems. HPCA 2000: 387-398 |
| c12 | | Tao Li, Lizy Kurian John, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Jyotsna Sabarinathan, Anupama Murthy: Using complete system simulation to characterize SPECjvm98 benchmarks. ICS 2000: 22-33 |
| c11 | | Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye: Energy-driven integrated hardware-software optimizations using SimplePower. ISCA 2000: 95-106 |
| c10 | | G. Esakkimuthu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Memory system energy (poster session): influence of hardware-software optimizations. ISLPED 2000: 244-246 |
| c9 | | Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Hyun Suk Kim: Experimental Evaluation of Energy Behavior of Iteration Space Tiling. LCPC 2000: 142-157 |
| c8 | | Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Hyun Suk Kim: Towards Energy-Aware Iteration Space Tiling. LCTES 2000: 211-215 |
| c7 | | Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam: A Holistic Approach to System Level Energy Optimization. PATMOS 2000: 88-107 |
| 1999 | ||
| c6 | | Narayanan Vijaykrishnan, N. Ranganathan: Tuning Branch Predictors to Support Virtual Method Invocation in Java. COOTS 1999: 217-228 |
| c5 | | Vamsi Krishna, N. Ranganathan, Narayanan Vijaykrishnan: Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages. VLSI Design 1999: 440- |
| 1998 | ||
| j1 | | Nagarajan Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar: A linear array processor with dynamic frequency clocking for image processing applications. IEEE Trans. Circuits Syst. Video Techn. 8(4): 435-445 (1998) |
| c4 | | Narayanan Vijaykrishnan, N. Ranganathan, Ravi Gadekarla: Object-Oriented Architectural Support for a Java Processor. ECOOP 1998: 330-354 |
| 1996 | ||
| c3 | | N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar: A VLSI array architecture with dynamic frequency clocking. ICCD 1996: 137-140 |
| c2 | | Narayanan Vijaykrishnan, Nagarajan Ranganathan, N. Bhavanishankar: DFLAP: a dynamic frequency linear array processor. ICIP (2) 1996: 1007-1010 |
| c1 | | Narayanan Vijaykrishnan, N. Ranganathan: SUBGEN: a genetic approach for subcircuit extraction. VLSI Design 1996: 343-345 |
Colors in the list of coauthors
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