Víctor Viñals Yúfera
List of publications from the DBLP Bibliography Server - FAQ| 2013 | ||
|---|---|---|
| j14 | Jorge Albericio, Pablo Ibáñez, Víctor Viñals, José María Llabería: Exploiting reuse locality on inclusive shared last-level caches. TACO 9(4): 38 (2013) | |
| c25 | Alexandra Ferrerón-Labari, Marta Ortín-Obón, Darío Suárez Gracia, Jesús Alastruey-Benedé, Víctor Viñals Yúfera: Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors. ARCS 2013: 256-267 | |
| 2012 | ||
| j13 | Benjamín Sahelices Fernández, Agustín De Dios Hernández, Pablo Ibáñez, Víctor Viñals Yúfera, José María Llabería: Effcient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence Controllers. J. Comput. Sci. Technol. 27(1): 75-91 (2012) | |
| j12 | Jorge Albericio, Ruben Gran Tejero, Pablo Ibáñez, Víctor Viñals, José María Llabería: ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache. TACO 8(4): 19 (2012) | |
| j11 | Darío Suárez Gracia, Giorgos Dimitrakopoulos, Teresa Monreal Arnal, Manolis Katevenis, Víctor Viñals Yúfera: LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors. IEEE Trans. VLSI Syst. 20(8): 1510-1523 (2012) | |
| c24 | Juan Segarra, Clemente Rodríguez, Ruben Gran Tejero, Luis C. Aparicio, Víctor Viñals: A Small and Effective Data Cache for Real-Time Multitasking Systems. IEEE Real-Time and Embedded Technology and Applications Symposium 2012: 45-54 | |
| 2011 | ||
| j10 | Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals: Multi-level Adaptive Prefetching based on Performance Gradient Tracking. J. Instruction-Level Parallelism 13 (2011) | |
| j9 | Luis C. Aparicio, Juan Segarra, Clemente Rodríguez, Víctor Viñals: Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems. Journal of Systems Architecture - Embedded Systems Design 57(7): 695-706 (2011) | |
| j8 | Ana Bosque, Víctor Viñals, Pablo Ibáñez, José M. Llabería: Filtering directory lookups in CMPs. Microprocessors and Microsystems - Embedded Hardware Design 35(8): 695-707 (2011) | |
| c23 | Ana Bosque, Víctor Viñals, Pablo Ibáñez, José María Llabería: Filtering Directory Lookups in CMPs with Write-Through Caches. Euro-Par (1) 2011: 269-281 | |
| 2010 | ||
| c22 | Ana Bosque, Víctor Viñals, Pablo Ibáñez, José M. Llabería: Filtering Directory Lookups in CMPs. DSD 2010: 207-216 | |
| c21 | Luis C. Aparicio, Juan Segarra, Clemente Rodríguez, Víctor Viñals: Combining Prefetch with Instruction Cache Locking in Multitasking Real-Time Systems. RTCSA 2010: 319-328 | |
| 2009 | ||
| j7 | Enrique F. Torres, Pablo Ibáñez, Víctor Viñals Yúfera, José María Llabería: Store Buffer Design for Multibanked Data Caches. IEEE Trans. Computers 58(10): 1307-1320 (2009) | |
| c20 | Darío Suárez Gracia, Teresa Monreal, Fernando Vallejo, Ramón Beivide, Víctor Viñals: Light NUCA: A proposal for bridging the inter-cache latency gap. DATE 2009: 530-535 | |
| c19 | Benjamín Sahelices Fernández, Pablo Ibáñez, Víctor Viñals, José María Llabería: A Methodology to Characterize Critical Section Bottlenecks in DSM Multiprocessors. Euro-Par 2009: 149-161 | |
| 2008 | ||
| c18 | Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals: Low-Cost Adaptive Data Prefetching. Euro-Par 2008: 327-336 | |
| c17 | Luis C. Aparicio, Juan Segarra, Clemente Rodríguez, J. L. Villarroel, Víctor Viñals: Avoiding the WCET Overestimation on LRU Instruction Cache. RTCSA 2008: 393-398 | |
| c16 | Jesús Alastruey, Teresa Monreal, Francisco J. Cazorla, Víctor Viñals, Mateo Valero: Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. SBAC-PAD 2008: 63-70 | |
| 2007 | ||
| j6 | Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals: Data prefetching in a cache hierarchy with high bandwidth and capacity. SIGARCH Computer Architecture News 35(4): 37-44 (2007) | |
| c15 | Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero: Microarchitectural Support for Speculative Register Renaming. IPDPS 2007: 1-10 | |
| c14 | Alicia Asín Pérez, Darío Suárez Gracia, Víctor Viñals Yúfera: A proposal to introduce power and energy notions in computer architecture laboratories. WCAE 2007: 52-57 | |
| 2006 | ||
| j5 | Jesús Alastruey, José Luis Briz, Pablo Ibáñez, Víctor Viñals: Software Demand, Hardware Supply. IEEE Micro 26(4): 72-82 (2006) | |
| c13 | Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero: Speculative early register release. Conf. Computing Frontiers 2006: 291-302 | |
| c12 | Agustín De Dios Hernández, Benjamín Sahelices Fernández, Pablo Ibáñez, Víctor Viñals, José M. Llabería: Speeding-Up Synchronizations in DSM Multiprocessors. Euro-Par 2006: 473-484 | |
| 2005 | ||
| j4 | Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero: Hardware support for early register release. IJHPCN 3(2/3): 83-94 (2005) | |
| j3 | María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas: Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors. TACO 2(3): 247-279 (2005) | |
| c11 | Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería: Store Buffer Design in First-Level Multibanked Data Caches. ISCA 2005: 469-480 | |
| 2004 | ||
| j2 | Teresa Monreal, Víctor Viñals, José González, Antonio González, Mateo Valero: Late Allocation and Early Release of Physical Registers. IEEE Trans. Computers 53(10): 1244-1259 (2004) | |
| c10 | Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería: Contents Management in First-Level Multibanked Data Caches. Euro-Par 2004: 516-524 | |
| 2003 | ||
| c9 | María Jesús Garzarán, Milos Prvulovic, Víctor Viñals, José María Llabería, Lawrence Rauchwerger, Josep Torrellas: Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation. IEEE PACT 2003: 170-181 | |
| c8 | Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería: Counteracting Bank Misprediction in Sliced First-Level Caches. Euro-Par 2003: 586-596 | |
| c7 | María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas: Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors. HPCA 2003: 191-202 | |
| 2002 | ||
| c6 | Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero: Hardware Schemes for Early Register Release. ICPP 2002: 5-13 | |
| 2001 | ||
| c5 | María Jesús Garzarán, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals: Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware. PDP 2001: 345-354 | |
| 2000 | ||
| j1 | Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals: Dynamic Register Renaming Through Virtual-Physical Registers. J. Instruction-Level Parallelism 2 (2000) | |
| c4 | Luis M. Ramos, Pablo E. Ibáñez, Víctor Viñals, José M. Llabería: Modeling load address behaviour through recurrences. ISPASS 2000: 101-108 | |
| 1999 | ||
| c3 | Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals: Delaying Physical Register Allocation through Virtual-Physical Registers. MICRO 1999: 186- | |
| 1998 | ||
| c2 | Pablo Ibáñez, Víctor Viñals, José Luis Briz, María Jesús Garzarán: Characterization and Improvement of Load/Store Cache-based Prefetching. International Conference on Supercomputing 1998: 369-376 | |
| 1996 | ||
| c1 | Pablo Ibáñez, Víctor Viñals: Performance Assessment of Contents Management in Multilevel On-Chip Caches. EUROMICRO 1996: 431-440 | |
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