Ramakrishnan Venkatraman

R. Venkatraman

	2012
c15		Ramamurthy Vishweshwara, Nagabhiru Mahita, Ramakrishnan Venkatraman: Placement aware clock gate cloning and redistribution methodology. ISQED 2012: 432-436
c14		Srinivas Vooka, Khushboo Agarwal, Abhijeet Shrivastava, Pranav Murthy, Ramakrishnan Venkatraman: A Silicon Testing Strategy for Pulse-Width Failures. VLSI Design 2012: 352-357
	2011
c13		S. M. Stalin, Amit Brahme, Ramakrishnan Venkatraman, Ajoy Mandal: DFM: Impact analysis in a high performance design. ISQED 2011: 110-115
c12		Sreekanth Soman, Amit Brahme, Ramakrishnan Venkatraman, Raashid Shaikh, Santhosh Thiyagaraja, Mahendrasing Patil: Ensuring On-Die Power Supply Robustness in High-Performance Designs. VLSI Design 2011: 220-225
	2009
c11		R. Venkatraman, R. Castagnetti, Andres Teene, Benjamin Mbouombouo, S. Ramesh: Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design. ISQED 2009: 27-32
c10		Parimala Viswanath, Pranav Murthy, Debajit Das, R. Venkatraman, Ajoy Mandal, Arvind Veeravalli, H. Udayakumar: Optimization strategies to improve statistical timing. ISQED 2009: 476-481
c9		Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, Vipul Kadodwala: Early clock prototyping for design analysis and quality entitlement. ISQED 2009: 641-646
c8		Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, H. Udayakumar, N. V. Arvind: An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis. VLSI Design 2009: 519-524
c7		R. Venkatraman, Shrikrishna Pundoor, Arun Koithyar, Madhusudan Rao, Jagdish C. Rao: Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions. VLSI Design 2009: 525-530
	2006
c6		R. Venkatraman, R. Castagnetti, S. Ramesh: The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability. ISQED 2006: 190-195
c5		Bhaskar J. Karmakar, V. Kalyana Chakravarty, R. Venkatraman, Jagdish C. Rao: Enabling Quality and Schedule Predictability in SoC Design using HandoffQC. ISQED 2006: 769-774
	2005
c4		R. Castagnetti, R. Venkatraman, B. Bartz, C. Monzel, T. Briscoe, Andres Teene, S. Ramesh: A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC. ISQED 2005: 193-196
	2003
c3		F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, S. Ramesh: Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability. ISQED 2003: 119-124
	2002
c2		Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji: Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. VLSI Design 2002: 781-788
	2000
j1		R. Venkatraman, S. Venkatraman: Rule-based system application for a technical problem in inventory issue. AI in Engineering 14(2): 143-152 (2000)
c1		R. Venkatraman, Lalit M. Patnaik: An evolutionary approach to timing driven FPGA placement. ACM Great Lakes Symposium on VLSI 2000: 81-85

Coauthor Index

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