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 | 2012 | |
|---|---|---|
| c16 |      | Chetan Vudadha, Sai Phaneendra P., Sreehari Veeramachaneni, Syed Ershad Ahmed, N. Moorthy Muthukrishnan, Mandalika B. Srinivas: Design of Prefix-Based Optimal Reversible Comparator. ISVLSI 2012: 201-206 |
| c15 | | Chetan Vudadha, Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas: Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders. ISVLSI 2012: 225-230 |
| c14 | | Chetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas: Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. VLSI Design 2012: 280-285 |
| 2011 | ||
| c13 | | Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas: A Unified Architecture for BCD and Binary Adder/Subtractor. DSD 2011: 426-429 |
| c12 | | Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas: A Prefix Based Reconfigurable Adder. ISVLSI 2011: 349-350 |
| 2010 | ||
| j2 | | Sandeep Saini, A. Mahesh Kumar, Sreehari Veeramachaneni, M. B. Srinivas: An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. J. Low Power Electronics 6(3): 429-435 (2010) |
| c11 | | Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas: A low power, variable resolution two-step flash ADC. ACM Great Lakes Symposium on VLSI 2010: 39-44 |
| c10 | | Mahesh Kumar Adimulam, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas: A Novel, Variable Resolution Flash ADC with Sub Flash Architecture. ISVLSI 2010: 434-435 |
| c9 | | Sandeep Saini, Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas: An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. VLSI Design 2010: 411-416 |
| 2009 | ||
| j1 | | Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas: A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter. J. Low Power Electronics 5(3): 279-290 (2009) |
| c8 | | Anshul Singh, Aman Gupta, Sreehari Veeramachaneni, M. B. Srinivas: A High Performance Unified BCD and Binary Adder/Subtractor. ISVLSI 2009: 211-216 |
| c7 | | Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas: A novel low power, variable resolution pipelined ADC. SoCC 2009: 183-186 |
| c6 | | Sreehari Veeramachaneni, Mahesh Kumar Adimulam, Venkat Tummala, M. B. Srinivas: Design of a Low Power, Variable-Resolution Flash ADC. VLSI Design 2009: 117-122 |
| 2008 | ||
| c5 | | Sreehari Veeramachaneni, Kirthi M. Krishna, Prateek G. V., Subroto S., Bharat S., M. B. Srinivas: A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor. VLSI Design 2008: 547-552 |
| 2007 | ||
| c4 | | Sreehari Veeramachaneni, Lingamneni Avinash, Kirthi M. Krishna, M. B. Srinivas: Novel architectures for efficient (m, n) parallel counters. ACM Great Lakes Symposium on VLSI 2007: 188-191 |
| c3 | | Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas: Novel High-Speed Redundant Binary to Binary converter using Prefix Networks. ISCAS 2007: 3271-3274 |
| c2 | | Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas: Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format. ISVLSI 2007: 343-350 |
| c1 | | Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas: Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors. VLSI Design 2007: 324-329 |
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