Pavel Vasilyev Coauthor index pubzone.org

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DBLP keys2008
j1no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Anatol Slissenko, Pavel Vasilyev: Simulation of Timed Abstract State Machines with Predicate Logic Model-Checking. J. UCS 14(12): 1984-2006 (2008)
2006
c2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Pavel Vasilyev: Simulator for Real-Time Abstract State Machines. FORMATS 2006: 337-351
c1no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Pavel Vasilyev: Simulator for Real-Time Abstract State Machines. MSVVEIS 2006: 202-205

Coauthor Index

1Anatol Slissenko
[j1]
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