Kimiyoshi Usami

Hiroshi Nakamura, Weihan Wang, Yuya Ohta, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Mitaro Namiki: Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design. IEICE Transactions 96-C(4): 404-412 (2013)

Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano: A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. ASP-DAC 2012: 407-412

Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura: CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. FPL 2012: 543-546

Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura: Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT 2012: 293-296

Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura: Stepwise sleep depth control for run-time leakage power saving. ACM Great Lakes Symposium on VLSI 2012: 233-238

Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura: Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating. ISQED 2012: 625-632

Seidai Takeda, Kyundong Kim, Hiroshi Nakamura, Kimiyoshi Usami: Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model. IEICE Transactions 94-A(12): 2499-2509 (2011)

Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo: Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips. IEEE Micro 31(6): 6-18 (2011)

Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano: Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs. IEEE Trans. on CAD of Integrated Circuits and Systems 30(4): 520-533 (2011)

Tatsuya Yamamoto, Kazuei Hironaka, Yuki Hayakawa, Masayuki Kimura, Hideharu Amano, Kimiyoshi Usami: Dynamic V_DD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction. ARC 2011: 230-241

Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo: Geyser-2: The second prototype CPU with fine-grained run-time power gating. ASP-DAC 2011: 87-88

Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo: Cool Mega-Array: A highly energy efficient reconfigurable accelerator. FPT 2011: 1-8

Kimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura: On-chip detection methodology for break-even time of power gated function units. ISLPED 2011: 241-246

Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo: Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. ASP-DAC 2010: 369-370

Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura: Adaptive power gating for function units in a microprocessor. ISQED 2010: 29-37

Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano: Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. NOCS 2010: 61-68

Lei Zhao, Hui Xu, Naomi Seki, Yoshiki Saito, Yohei Hasegawa, Kimiyoshi Usami, Hideharu Amano: Cache Controller Design on Ultra Low Leakage Embedded Processors. ARCS 2009: 171-182

Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura: Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. VLSI Design 2009: 381-386

Jerry Frenkil, Ken Choi, Kimiyoshi Usami: Power Gating for Ultra-low Leakage: Physics, Design, and Analysis. DATE 2008

Yoshiki Saito, Tomoaki Shirai, Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami, Hideharu Amano: Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique. FPT 2008: 329-332

Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura: A fine-grain dynamic sleep control scheme in MIPS R3000. ICCD 2008: 612-617

Kimiyoshi Usami: Overview on Low Power SoC Design Technology. ASP-DAC 2007: 634-636

Naoaki Ohkubo, Kimiyoshi Usami: Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits. IEICE Transactions 89-A(12): 3482-3490 (2006)

Naoaki Ohkubo, Kimiyoshi Usami: Delay modeling and static timing analysis for MTCMOS circuits. ASP-DAC 2006: 570-575

Kimiyoshi Usami, Naoaki Ohkubo: A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals. ICCD 2006

Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak: Code Coverage-Based Power Estimation Techniques for Microprocessors. Journal of Circuits, Systems, and Computers 11(5): 557- (2002)

Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa: Automated selective multi-threshold design for ultra-low standby applications. ISLPED 2002: 202-206

Kimiyoshi Usami, Mutsunori Igarashi: Low-power design methodology and applications utilizing dual supply voltages. ASP-DAC 2000: 123-128

Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak: Function-level power estimation methodology for microprocessors. DAC 2000: 810-813

Takeshi Kitahara, Fumihiro Minami, Toshiaki Ueda, Kimiyoshi Usami, Seiichi Nishio, Masami Murakata, Takashi Mitsuhashi: A Clock-Gating Method for Low-Power LSI Design. ASP-DAC 1998: 307-312

Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa, Tadahiro Kuroda: Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques. DAC 1998: 483-488

Mutsunori Igarashi, Kimiyoshi Usami, Kazutaka Nogami, Fumihiro Minami, Yukio Kawasaki, Takahiro Aoki, Midori Takano, Chiharo Mizuno, Takashi Ishikawa, Masahiro Kanazawa, Shinji Sonoda, Makoto Ichida, Naoyuki Hatanaka: A low-power design method using multiple supply voltages. ISLPED 1997: 36-41

Kimiyoshi Usami, Mark Horowitz: Clustered voltage scaling technique for low-power design. ISLPD 1995: 3-8

Nobu Matsumoto, Yoko Watanabe, Kimiyoshi Usami, Yukio Sugeno, Hiroshi Hatada, Shojiro Mori: Datapath Generator Based on Gate-Level Symbolic Layout. DAC 1990: 388-393