Gary S. Tyson

Ian Finlayson, Gang-Ryung Uh, David B. Whalley, Gary S. Tyson: An Overview of Static Pipelining. Computer Architecture Letters 11(1): 17-20 (2012)

Daniel Chang, Stephen Hines, Paul E. West, Gary S. Tyson, David B. Whalley: Program Differentiation. Journal of Circuits, Systems, and Computers 21(2) (2012)

Ian Finlayson, Gang-Ryung Uh, David B. Whalley, Gary S. Tyson: Improving Low Power Processor Efficiency with Static Pipelining. Interaction between Compilers and Computer Architectures 2011: 17-24

Yue Li, Gary S. Tyson, Jinfeng Zhang: Effect of sequences on the shape of protein energy landscapes. BCB 2010: 35-42

Prasad A. Kulkarni, David B. Whalley, Gary S. Tyson, Jack W. Davidson: Practical exhaustive optimization phase order exploration and evaluation. TACO 6(1) (2009)

Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson: Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems. T. HiPEAC 2: 65-84 (2009)

Paul E. West, Yuval Peress, Gary S. Tyson, Sally A. McKee: Core monitors: monitoring performance in multicore processors. Conf. Computing Frontiers 2009: 31-40

Stephen Roderick Hines, Yuval Peress, Peter Gavin, David B. Whalley, Gary S. Tyson: Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE). LCTES 2009: 119-128

Renato J. O. Figueiredo, P. Oscar Boykin, José A. B. Fortes, Tao Li, Jie-Kwon Peir, David Wolinsky, Lizy K. John, David R. Kaeli, David J. Lilja, Sally A. McKee, Gokhan Memik, Alain Roy, Gary S. Tyson: Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education. CollaborateCom 2008: 70-84

David B. Whalley, Gary S. Tyson: Enhancing the effectiveness of utilizing an instruction register file. IPDPS 2008: 1-5

Renato J. O. Figueiredo, P. Oscar Boykin, José A. B. Fortes, Tao Li, Jie-Kwon Peir, David Wolinsky, Lizy Kurian John, David R. Kaeli, David J. Lilja, Sally A. McKee, Gokhan Memik, Alain Roy, Gary S. Tyson: Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education. CoRR abs/0807.1765 (2008)

Michael J. Geiger, Sally A. McKee, Gary S. Tyson: Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems. T. HiPEAC 1: 54-73 (2007)

Chris Zimmer, Stephen Roderick Hines, Prasad A. Kulkarni, Gary S. Tyson, David B. Whalley: Facilitating compiler optimizations through the dynamic mapping of alternate register structures. CASES 2007: 165-169

Prasad A. Kulkarni, David B. Whalley, Gary S. Tyson: Evaluating Heuristic Optimization Phase Order Search Algorithms. CGO 2007: 157-169

Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson: Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems. HiPEAC 2007: 23-37

Stephen Roderick Hines, Gary S. Tyson, David B. Whalley: Addressing instruction fetch bottlenecks by using an instruction register file. LCTES 2007: 165-174

Stephen Hines, David B. Whalley, Gary S. Tyson: Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache. MICRO 2007: 433-444

Allen C. Cheng, Gary S. Tyson: High-quality ISA synthesis for low-power cache designs in embedded microprocessors. IBM Journal of Research and Development 50(2-3): 299-310 (2006)

Stephen Hines, David B. Whalley, Gary S. Tyson: Adapting compilation techniques to enhance the packing of instructions into registers. CASES 2006: 43-53

Prasad A. Kulkarni, David B. Whalley, Gary S. Tyson, Jack W. Davidson: Exhaustive Optimization Phase Order Space Exploration. CGO 2006: 306-318

William C. Kreahling, Stephen Hines, David B. Whalley, Gary S. Tyson: Reducing the cost of conditional transfers of control by using comparison specifications. LCTES 2006: 64-71

Prasad A. Kulkarni, David B. Whalley, Gary S. Tyson, Jack W. Davidson: In search of near-optimal optimization phase orderings. LCTES 2006: 83-92

Allen C. Cheng, Gary S. Tyson: An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs. IEEE Trans. Computers 54(6): 698-713 (2005)

Michael J. Geiger, Sally A. McKee, Gary S. Tyson: Drowsy region-based caches: minimizing both dynamic and static power dissipation. Conf. Computing Frontiers 2005: 378-384

Michael J. Geiger, Sally A. McKee, Gary S. Tyson: Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation. HiPEAC 2005: 102-115

Stephen Hines, Joshua Green, Gary S. Tyson, David B. Whalley: Improving Program Efficiency by Packing Instructions into Registers. ISCA 2005: 260-271

Allen C. Cheng, Gary S. Tyson, Trevor N. Mudge: PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application Specific Instruction Set Synthesis. ISPASS 2005: 32-41

Stephen Hines, Gary S. Tyson, David B. Whalley: Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows. MICRO 2005: 19-29

Viji Srinivasan, Edward S. Davidson, Gary S. Tyson: A Prefetch Taxonomy. IEEE Trans. Computers 53(2): 126-140 (2004)

Allen C. Cheng, Gary S. Tyson, Trevor N. Mudge: FITS: framework-based instruction-set tuning synthesis for embedded application specific processors. DAC 2004: 920-923

Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens: Improving Bandwidth Utilization using Eager Writeback. J. Instruction-Level Parallelism 3 (2001)

Hsien-Hsin S. Lee, Mikhail Smelyanskiy, Chris J. Newburn, Gary S. Tyson: Stack Value File: Custom Microarchitecture for the Stack. HPCA 2001: 5-14

Viji Srinivasan, Edward S. Davidson, Gary S. Tyson, Mark J. Charney, Thomas R. Puzak: Branch History Guided Instruction Prefetching. HPCA 2001: 291-300

Edward S. Tam, Stevan A. Vlaovic, Gary S. Tyson, Edward S. Davidson: Allocation by Conflict: A Simple Effective Multilateral Cache Management Scheme. ICCD 2001: 133-141

Mikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson: Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining. IEEE PACT 2000: 3-12

Hsien-Hsin S. Lee, Gary S. Tyson: Region-based caching: an energy-delay efficient memory architecture for embedded processors. CASES 2000: 120-127

Murali Annavaram, Gary S. Tyson, Edward S. Davidson: Instruction overhead and data locality effects in superscalar processors. ISPASS 2000: 95-100

Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens: Eager writeback - a technique for improving bandwidth utilization. MICRO 2000: 11-21

Stevan A. Vlaovic, Edward S. Davidson, Gary S. Tyson: Improving BTB performance in the presence of DLLs. MICRO 2000: 77-86

Gary S. Tyson, Todd M. Austin: Memory Renaming: Fast, Early and Accurate Processing of Memory Communication. International Journal of Parallel Programming 27(5): 357-380 (1999)

Matt Postiff, Gary S. Tyson, Trevor N. Mudge: Performance Limits of Trace Caches. J. Instruction-Level Parallelism 1 (1999)

Matthew A. Postiff, David A. Greene, Gary S. Tyson, Trevor N. Mudge: The limits of instruction level parallelism in SPEC95 applications. SIGARCH Computer Architecture News 27(1): 31-34 (1999)

Krisztián Flautner, Gary S. Tyson, Trevor N. Mudge: A high level simulator integrated with the Mirv compiler. SIGARCH Computer Architecture News 27(1): 43-46 (1999)

Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson: Active Management of Data Caches by Exploiting Reuse Information. IEEE Trans. Computers 48(11): 1244-1259 (1999)

Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary S. Tyson, Todd M. Austin: Classifying load and store instructions for memory renaming. International Conference on Supercomputing 1999: 399-407

Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson: Evaluating the performance of active cache management schemes. ICCD 1998: 368-375

Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens: Utilizing Reuse Information in Data Cache Management. International Conference on Supercomputing 1998: 449-456

Edward S. Tam, Jude A. Rivers, Gary S. Tyson, Edward S. Davidson: mlcache: A Flexible Multi-Lateral Cache Simulator. MASCOTS 1998: 19-26

Sangwook P. Kim, Gary S. Tyson: Analyzing the Working Set Characteristics of Branch Execution. MICRO 1998: 49-58

Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun: Managing data caches using selective cache line replacement. International Journal of Parallel Programming 25(3): 213-242 (1997)

Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin: On High-Bandwidth Data Cache Design for Multi-Issue Processors. MICRO 1997: 46-56

Gary S. Tyson, Todd M. Austin: Improving the Accuracy and Performance of Memory Communication Through Renaming. MICRO 1997: 218-227

Gary S. Tyson, Matthew K. Farrens: Evaluating the Effects of Predicated Execution on Branch Prediction. International Journal of Parallel Programming 24(2): 159-186 (1996)

Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun: A modified approach to data cache management. MICRO 1995: 93-103

Gary S. Tyson, Matthew K. Farrens: Code scheduling for multiple instruction stream architectures. International Journal of Parallel Programming 22(3): 243-272 (1994)

Matthew K. Farrens, Gary S. Tyson, Andrew R. Pleszkun: A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors. ISCA 1994: 338-347

Gary S. Tyson: The effects of predicated execution on branch prediction. MICRO 1994: 196-206

Gary S. Tyson, Matthew K. Farrens: Techniques for extracting instruction level parallelism on MIMD architectures. MICRO 1993: 128-137

Gary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun: MISC: a Multiple Instruction Stream Computer. MICRO 1992: 193-196

Matthew K. Farrens, Arvin Park, Gary S. Tyson: Modifying VM hardware to reduce address pin requirements. MICRO 1992: 210-213