Shihheng Tsai

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	2012
c2		Shihheng Tsai, Man-Yu Li, Chung-Yang Huang: A semi-formal min-cost buffer insertion technique considering multi-mode multi-corner timing constraints. ASP-DAC 2012: 505-510
	2009
c1		Shihheng Tsai, Chung-Yang Huang: A false-path aware formal static timing analyzer considering simultaneous input transitions. DAC 2009: 25-30

Coauthor Index

1	Chung-Yang Huang (Chung-Yang (Ric) Huang)	[c2] [c1]
2	Man-Yu Li	[c2]

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