DBLP: Adonios Thanailakis

	2010
j34		Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis: A Novel Allocation Methodology for Partial and Dynamic Bitstream Generation for FPGA Architectures. Journal of Circuits, Systems, and Computers 19(3): 701-717 (2010)
	2008
j33		Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis: Designing a General-Purpose Interconnection Architecture for Field Programmable Gate Arrays. J. Low Power Electronics 4(1): 34-47 (2008)
j32		Minas Dasygenis, K. Mitroglou, Dimitrios Soudris, Adonios Thanailakis: A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System. IEEE Trans. on Circuits and Systems 55-I(2): 546-558 (2008)
j31		Vasilios A. Mardiris, Georgios Ch. Sirakoulis, Ch. Mizas, Ioannis Karafyllidis, Adonios Thanailakis: A CAD System for Modeling and Simulation of Computer Networks Using Cellular Automata. IEEE Transactions on Systems, Man, and Cybernetics, Part C 38(2): 253-264 (2008)
	2007
j30		Marios Kesoulis, Dimitrios Soudris, Christos S. Koukourlis, Adonios Thanailakis: Systematic methodology for designing low power direct digital frequency synthesisers. IET Circuits, Devices & Systems 1(4): 293-304 (2007)
j29		Konstantinos Tatas, George Koutroumpezis, Dimitrios Soudris, Adonios Thanailakis: Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications. Integration 40(2): 74-93 (2007)
j28		Stylianos Mamagkakis, Alexandros Bartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: Systematic methodology for exploration of performance - Energy trade-offs in network applications using Dynamic Data Type refinement. Journal of Systems Architecture 53(7): 417-436 (2007)
c34		Kostas Siozios, Stelios Mamagkakis, Dimitrios Soudris, Antonios Thanailakis: Designing Heterogeneous FPGAs with Multiple SBs. ARC 2007: 91-96
i1		Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck. CoRR abs/0710.4656 (2007)
	2006
j27		Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance. Computer Communications 29(13-14): 2612-2620 (2006)
j26		Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Adonios Thanailakis: A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck. IEEE Trans. VLSI Syst. 14(3): 279-291 (2006)
j25		Nikolas Kroupis, Nikolaos D. Zervas, Minas Dasygenis, Konstantinos Tatas, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis: Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors. VLSI Signal Processing 44(1-2): 153-171 (2006)
c33		Alexandros Bartzas, Stylianos Mamagkakis, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications. DATE 2006: 740-745
c32		K. Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis: A novel methodology for designing high-performance and low-energy FPGA routing architecture. FPGA 2006: 224
c31		Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications. IPDPS 2006
c30		Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis: A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications. ISCAS 2006
c29		Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis: Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources. PATMOS 2006: 403-414
c28		Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis: Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique. VLSI-SoC 2006: 204-209
	2005
j24		Georgios Ch. Sirakoulis, V. Raptis, Ioannis Karafyllidis, Phillipos Tsalides, Adonios Thanailakis: A fault-tolerant message passing algorithm and its hardware implementation. Advances in Engineering Software 36(3): 159-171 (2005)
j23		Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis: A cellular automaton for the propagation of circular fronts and its applications. Eng. Appl. of AI 18(6): 731-744 (2005)
j22		Kostas Siozios, George Koutroumpezis, Konstantinos Tatas, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Dimitrios Soudris, Antonios Thanailakis, Spiridon Nikolaidis, Stilianos Siskos: A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications. IEICE Transactions 88-D(7): 1369-1380 (2005)
j21		Konstantinos Tatas, Dimitrios Soudris, D. Siomos, Adonios Thanailakis: A Novel Division Algorithm and Architectures for Parallel and Sequential Processing. Journal of Circuits, Systems, and Computers 14(2): 281-296 (2005)
j20		Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms. J. Embedded Computing 1(3): 353-362 (2005)
c27		Dimitrios Soudris, Spiridon Nikolaidis, Stilianos Siskos, Konstantinos Tatas, K. Siozios, George Koutroumpezis, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Adonios Thanailakis: AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow. ASP-DAC 2005: 3-4
c26		Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck. DATE 2005: 946-947
c25		Kostas Siozios, Konstantinos Tatas, George Koutroumpezis, D. J. Soudris, Adonios Thanailakis: An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform. FPL 2005: 658-661
c24		Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis: A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow. FPL 2005: 707-708
c23		Kostas Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation. IPDPS 2005
c22		Nikolas Kroupis, Minas Dasygenis, K. Markou, Dimitrios Soudris, Adonios Thanailakis: A modified spiral search motion estimation algorithm and its embedded system implementation. ISCAS (4) 2005: 3347-3350
c21		Minas Dasygenis, Erik Brockmeyer, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: Improving the Memory Bandwidth Utilization Using Loop Transformations. PATMOS 2005: 117-126
c20		Nikolas Kroupis, Minas Dasygenis, Dimitrios Soudris, Antonios Thanailakis: A Modified Spiral Search Algorithm and its Embedded Hardware Implementation. IEC (Prague) 2005: 375-378
c19		Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, José M. Mendías, Antonios Thanailakis: Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications. WWIC 2005: 354-364
	2004
j19		Ioannis Tsimperidis, Ioannis Karafyllidis, Antonios Thanailakis: Design and simulation of a nanoelectronic single-electron universal Control-Control-Not gate. Microelectronics Journal 35(5): 471-478 (2004)
c18		K. Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development. FPL 2004: 1116-1118
c17		Vasilios Kalenteridis, Haroula Pournara, K. Siozios, Konstantinos Tatas, George Koutroumpezis, Ilias Pappas, Spiridon Nikolaidis, Stilianos Siskos, D. J. Soudris, Adonios Thanailakis: An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development. IPDPS 2004
c16		Evaggelia Theochari, Konstantinos Tatas, Dimitrios Soudris, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas, Antonios Thanailakis: A reusable IP FFT core for DSP applications. ISCAS (3) 2004: 621-624
c15		Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications. SAMOS 2004: 540-549
c14		Stylianos Mamagkakis, Alexandros Mpartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias, Antonios Thanailakis: Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology. WWIC 2004: 26-37
	2003
j18		Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Ch. Mizas, Vasilios A. Mardiris, Adonios Thanailakis, Phillipos Tsalides: A cellular automaton model for the study of DNA sequence evolution. Comp. in Bio. and Med. 33(5): 439-453 (2003)
j17		Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis: A CAD system for the construction and VLSI implementation of Cellular Automata algorithms using VHDL. Microprocessors and Microsystems 27(8): 381-396 (2003)
j16		Konstantinos Tatas, Minas Dasygenis, Nikolas Kroupis, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis: Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms. Real-Time Imaging 9(6): 371-386 (2003)
c13		Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis: Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms. FPL 2003: 1032-1035
c12		Dimitrios Soudris, Marios Kesoulis, Christos S. Koukourlis, Adonios Thanailakis, Spyros Blionas: Alternative Direct Digital Frequency Synthesizer architectures with reduced memory size. ISCAS (2) 2003: 73-76
c11		Dimitrios Soudris, K. Sgouropoulos, Konstantinos Tatas, Vasilis F. Pavlidis, Adonios Thanailakis: A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems. ISCAS (5) 2003: 129-132
c10		Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas: Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms. PATMOS 2003: 430-439
c9		Konstantinos Tatas, K. Siozios, Nikolaos Vassiliadis, D. J. Soudris, Spiridon Nikolaidis, Stilianos Siskos, Adonios Thanailakis: FPGA Architecture Design and Toolset for Logic Implementation. PATMOS 2003: 607-616
c8		Marios Kesoulis, Dimitrios Soudris, Christos S. Koukourlis, Adonios Thanailakis: Designing Low Power Direct Digital Frequency Synthesizers. VLSI-SOC 2003: 105-110
	2002
j15		Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis: A cellular automaton methodology for the simulation of integrated circuit fabrication processes. Future Generation Comp. Syst. 18(5): 639-657 (2002)
j14		S. Theoharis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis, Adonios Thanailakis: A fast and accurate delay dependent method for switching estimation of large combinational circuits. Journal of Systems Architecture 48(4-5): 113-124 (2002)
c7		George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios Thanailakis: Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. FPL 2002: 1027-1036
	2001
c6		Nikolas Kroupis, Minas Dasygenis, Antonios Argyriou, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis, Nikolaos D. Zervas, Constantinos E. Goutis: Power, performance and area exploration of block matching algorithms mapped on programmable processors. ICIP (3) 2001: 728-731
c5		I. Thoidis, Dimitrios Soudris, J. M. Fernandez, Adonios Thanailakis: The circuit design of multiple-valued logic voltage-mode adders. ISCAS (4) 2001: 162-165
c4		D. J. Soudris, M. M. Dasigenis, S. K. Vasilopoulou, Adonios Thanailakis: A CAD tool for architecture level exploration and automatic generation of RNS converters. ISCAS (4) 2001: 730-733
	2000
c3		Dimitrios Soudris, Nikolaos D. Zervas, Antonios Argyriou, Minas Dasygenis, Konstantinos Tatas, Constantinos E. Goutis, Adonios Thanailakis: Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications. PATMOS 2000: 243-254
	1999
c2		M. Perakis, A. E. Tzimas, E. G. Metaxakis, Dimitrios Soudris, Grigorios A. Kalivas, C. Katis, Chrissavgi Dre, Constantinos E. Goutis, Adonios Thanailakis, Thanos Stouraitis: The VLSI implementation of a baseband receiver for DECT-based portable applications. ISCAS (1) 1999: 198-201
	1998
c1		I. Thoidis, Dimitrios Soudris, Ioannis Karafyllidis, Adonios Thanailakis, Thanos Stouraitis: Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic. Great Lakes Symposium on VLSI 1998: 83-88
	1997
j13		Panagiotis Tzionas, Adonios Thanailakis, Phillipos G. Tsalides: An efficient algorithm for the largest empty figure problem based on a 2D cellular automaton architecture. Image Vision Comput. 15(1): 35-45 (1997)
j12		Ioannis Karafyllidis, A. Ioannidis, Adonios Thanailakis, Phillipos Tsalides: Geometrical Shape Recognition Using a Cellular Automaton Architecture and its VLSI Implementation. Real-Time Imaging 3(4): 243-254 (1997)
	1996
j11		Panagiotis Tzionas, Antonios Thanailakis, Phillipos Tsalides: A hybrid cellular automaton/neural network classifier for multi-valued patterns and its VLSI implementation. Integration 20(2): 211-237 (1996)
j10		Ioannis Andreadis, Ioannis Karafyllidis, Panagiotis Tzionas, Adonios Thanailakis, Phillipos Tsalides: A new hardware module for automated visual inspection based on a cellular automaton architecture. Journal of Intelligent and Robotic Systems 16(1): 89-102 (1996)
j9		Ioannis Karafyllidis, Ioannis Andreadis, Panagiotis Tzionas, Phillipos G. Tsalides, Adonios Thanailakis: A cellular automaton for the determination of the mean velocity of moving objects and its VLSI implementation. Pattern Recognition 29(4): 689-699 (1996)
	1995
j8		Panagiotis Tzionas, Phillipos G. Tsalides, Adonios Thanailakis: A Parallel Skeletonization Algorithm Based on Two-Dimensional Cellular Automata and its VLSI Implementation. Real-Time Imaging 1(2): 105-117 (1995)
	1994
j7		E. D. Adamides, Phillipos G. Tsalides, Adonios Thanailakis: Bit-serial VLSI sorter with high reliability specifications. Microprocessing and Microprogramming 40(8): 523-536 (1994)
j6		Panagiotis Tzionas, Panagiotis G. Tsalides, Adonios Thanailakis: A new, cellular automaton-based, nearest neighbor pattern classifier and its VLSI implementation. IEEE Trans. VLSI Syst. 2(3): 343-353 (1994)
	1993
j5		Panagiotis Tzionas, Phillipos Tsalides, Antonios Thanailakis: 2-Dimensional minimum cost path planning using a cellular automaton architecture. Integration 16(2): 179-194 (1993)
	1992
j4		E. D. Adamides, Phillipos Tsalides, Adonios Thanailakis: Hierarchical Cellular Automata structures. Parallel Computing 18(5): 517-524 (1992)
	1989
j3		E. D. Adamides, Phillipos Tsalides, Adonios Thanailakis: Synchronization of D. Parkinsonasynchronous concurrent processes using cellular automata. Parallel Computing 11(2): 163-169 (1989)
	1986
j2		Howard C. Card, Adonios Thanailakis, Werner Pries, Robert D. McLeod: Analysis of Bounded Linear Cellular Automata Based on a Method of Image Charges. J. Comput. Syst. Sci. 33(3): 473-480 (1986)
j1		Werner Pries, Adonios Thanailakis, Howard C. Card: Group Properties of Cellular Automata and VLSI Applications. IEEE Trans. Computers 35(12): 1013-1024 (1986)

2010

j34

Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis: A Novel Allocation Methodology for Partial and Dynamic Bitstream Generation for FPGA Architectures. Journal of Circuits, Systems, and Computers 19(3): 701-717 (2010)

2008

j33

Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis: Designing a General-Purpose Interconnection Architecture for Field Programmable Gate Arrays. J. Low Power Electronics 4(1): 34-47 (2008)

j32

Minas Dasygenis, K. Mitroglou, Dimitrios Soudris, Adonios Thanailakis: A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System. IEEE Trans. on Circuits and Systems 55-I(2): 546-558 (2008)

j31

Vasilios A. Mardiris, Georgios Ch. Sirakoulis, Ch. Mizas, Ioannis Karafyllidis, Adonios Thanailakis: A CAD System for Modeling and Simulation of Computer Networks Using Cellular Automata. IEEE Transactions on Systems, Man, and Cybernetics, Part C 38(2): 253-264 (2008)

2007

j30

Marios Kesoulis, Dimitrios Soudris, Christos S. Koukourlis, Adonios Thanailakis: Systematic methodology for designing low power direct digital frequency synthesisers. IET Circuits, Devices & Systems 1(4): 293-304 (2007)

j29

Konstantinos Tatas, George Koutroumpezis, Dimitrios Soudris, Adonios Thanailakis: Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications. Integration 40(2): 74-93 (2007)

j28

Stylianos Mamagkakis, Alexandros Bartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: Systematic methodology for exploration of performance - Energy trade-offs in network applications using Dynamic Data Type refinement. Journal of Systems Architecture 53(7): 417-436 (2007)

c34

Kostas Siozios, Stelios Mamagkakis, Dimitrios Soudris, Antonios Thanailakis: Designing Heterogeneous FPGAs with Multiple SBs. ARC 2007: 91-96

Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck. CoRR abs/0710.4656 (2007)

2006

j27

Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance. Computer Communications 29(13-14): 2612-2620 (2006)

j26

Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Adonios Thanailakis: A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck. IEEE Trans. VLSI Syst. 14(3): 279-291 (2006)

j25

Nikolas Kroupis, Nikolaos D. Zervas, Minas Dasygenis, Konstantinos Tatas, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis: Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors. VLSI Signal Processing 44(1-2): 153-171 (2006)

c33

Alexandros Bartzas, Stylianos Mamagkakis, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications. DATE 2006: 740-745

c32

K. Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis: A novel methodology for designing high-performance and low-energy FPGA routing architecture. FPGA 2006: 224

c31

Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications. IPDPS 2006

c30

Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis: A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications. ISCAS 2006

c29

Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis: Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources. PATMOS 2006: 403-414

c28

Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis: Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique. VLSI-SoC 2006: 204-209

2005

j24

Georgios Ch. Sirakoulis, V. Raptis, Ioannis Karafyllidis, Phillipos Tsalides, Adonios Thanailakis: A fault-tolerant message passing algorithm and its hardware implementation. Advances in Engineering Software 36(3): 159-171 (2005)

j23

Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis: A cellular automaton for the propagation of circular fronts and its applications. Eng. Appl. of AI 18(6): 731-744 (2005)

j22

Kostas Siozios, George Koutroumpezis, Konstantinos Tatas, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Dimitrios Soudris, Antonios Thanailakis, Spiridon Nikolaidis, Stilianos Siskos: A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications. IEICE Transactions 88-D(7): 1369-1380 (2005)

j21

Konstantinos Tatas, Dimitrios Soudris, D. Siomos, Adonios Thanailakis: A Novel Division Algorithm and Architectures for Parallel and Sequential Processing. Journal of Circuits, Systems, and Computers 14(2): 281-296 (2005)

j20

Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms. J. Embedded Computing 1(3): 353-362 (2005)

c27

Dimitrios Soudris, Spiridon Nikolaidis, Stilianos Siskos, Konstantinos Tatas, K. Siozios, George Koutroumpezis, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Adonios Thanailakis: AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow. ASP-DAC 2005: 3-4

c26

c25

Kostas Siozios, Konstantinos Tatas, George Koutroumpezis, D. J. Soudris, Adonios Thanailakis: An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform. FPL 2005: 658-661

c24

Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis: A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow. FPL 2005: 707-708

c23

Kostas Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation. IPDPS 2005

c22

Nikolas Kroupis, Minas Dasygenis, K. Markou, Dimitrios Soudris, Adonios Thanailakis: A modified spiral search motion estimation algorithm and its embedded system implementation. ISCAS (4) 2005: 3347-3350

c21

Minas Dasygenis, Erik Brockmeyer, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: Improving the Memory Bandwidth Utilization Using Loop Transformations. PATMOS 2005: 117-126

c20

Nikolas Kroupis, Minas Dasygenis, Dimitrios Soudris, Antonios Thanailakis: A Modified Spiral Search Algorithm and its Embedded Hardware Implementation. IEC (Prague) 2005: 375-378

c19

Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, José M. Mendías, Antonios Thanailakis: Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications. WWIC 2005: 354-364

2004

j19

Ioannis Tsimperidis, Ioannis Karafyllidis, Antonios Thanailakis: Design and simulation of a nanoelectronic single-electron universal Control-Control-Not gate. Microelectronics Journal 35(5): 471-478 (2004)

c18

K. Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development. FPL 2004: 1116-1118

c17

Vasilios Kalenteridis, Haroula Pournara, K. Siozios, Konstantinos Tatas, George Koutroumpezis, Ilias Pappas, Spiridon Nikolaidis, Stilianos Siskos, D. J. Soudris, Adonios Thanailakis: An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development. IPDPS 2004

c16

Evaggelia Theochari, Konstantinos Tatas, Dimitrios Soudris, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas, Antonios Thanailakis: A reusable IP FFT core for DSP applications. ISCAS (3) 2004: 621-624

c15

Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications. SAMOS 2004: 540-549

c14

Stylianos Mamagkakis, Alexandros Mpartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias, Antonios Thanailakis: Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology. WWIC 2004: 26-37

2003

j18

Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Ch. Mizas, Vasilios A. Mardiris, Adonios Thanailakis, Phillipos Tsalides: A cellular automaton model for the study of DNA sequence evolution. Comp. in Bio. and Med. 33(5): 439-453 (2003)

j17

Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis: A CAD system for the construction and VLSI implementation of Cellular Automata algorithms using VHDL. Microprocessors and Microsystems 27(8): 381-396 (2003)

j16

Konstantinos Tatas, Minas Dasygenis, Nikolas Kroupis, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis: Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms. Real-Time Imaging 9(6): 371-386 (2003)

c13

Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis: Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms. FPL 2003: 1032-1035

c12

Dimitrios Soudris, Marios Kesoulis, Christos S. Koukourlis, Adonios Thanailakis, Spyros Blionas: Alternative Direct Digital Frequency Synthesizer architectures with reduced memory size. ISCAS (2) 2003: 73-76

c11

Dimitrios Soudris, K. Sgouropoulos, Konstantinos Tatas, Vasilis F. Pavlidis, Adonios Thanailakis: A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems. ISCAS (5) 2003: 129-132

c10

Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas: Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms. PATMOS 2003: 430-439

Konstantinos Tatas, K. Siozios, Nikolaos Vassiliadis, D. J. Soudris, Spiridon Nikolaidis, Stilianos Siskos, Adonios Thanailakis: FPGA Architecture Design and Toolset for Logic Implementation. PATMOS 2003: 607-616

Marios Kesoulis, Dimitrios Soudris, Christos S. Koukourlis, Adonios Thanailakis: Designing Low Power Direct Digital Frequency Synthesizers. VLSI-SOC 2003: 105-110

2002

j15

Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis: A cellular automaton methodology for the simulation of integrated circuit fabrication processes. Future Generation Comp. Syst. 18(5): 639-657 (2002)

j14

S. Theoharis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis, Adonios Thanailakis: A fast and accurate delay dependent method for switching estimation of large combinational circuits. Journal of Systems Architecture 48(4-5): 113-124 (2002)

George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios Thanailakis: Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. FPL 2002: 1027-1036

2001

Nikolas Kroupis, Minas Dasygenis, Antonios Argyriou, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis, Nikolaos D. Zervas, Constantinos E. Goutis: Power, performance and area exploration of block matching algorithms mapped on programmable processors. ICIP (3) 2001: 728-731

I. Thoidis, Dimitrios Soudris, J. M. Fernandez, Adonios Thanailakis: The circuit design of multiple-valued logic voltage-mode adders. ISCAS (4) 2001: 162-165

D. J. Soudris, M. M. Dasigenis, S. K. Vasilopoulou, Adonios Thanailakis: A CAD tool for architecture level exploration and automatic generation of RNS converters. ISCAS (4) 2001: 730-733

2000

Dimitrios Soudris, Nikolaos D. Zervas, Antonios Argyriou, Minas Dasygenis, Konstantinos Tatas, Constantinos E. Goutis, Adonios Thanailakis: Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications. PATMOS 2000: 243-254

1999

M. Perakis, A. E. Tzimas, E. G. Metaxakis, Dimitrios Soudris, Grigorios A. Kalivas, C. Katis, Chrissavgi Dre, Constantinos E. Goutis, Adonios Thanailakis, Thanos Stouraitis: The VLSI implementation of a baseband receiver for DECT-based portable applications. ISCAS (1) 1999: 198-201

1998

I. Thoidis, Dimitrios Soudris, Ioannis Karafyllidis, Adonios Thanailakis, Thanos Stouraitis: Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic. Great Lakes Symposium on VLSI 1998: 83-88

1997

j13

Panagiotis Tzionas, Adonios Thanailakis, Phillipos G. Tsalides: An efficient algorithm for the largest empty figure problem based on a 2D cellular automaton architecture. Image Vision Comput. 15(1): 35-45 (1997)

j12

Ioannis Karafyllidis, A. Ioannidis, Adonios Thanailakis, Phillipos Tsalides: Geometrical Shape Recognition Using a Cellular Automaton Architecture and its VLSI Implementation. Real-Time Imaging 3(4): 243-254 (1997)

1996

j11

Panagiotis Tzionas, Antonios Thanailakis, Phillipos Tsalides: A hybrid cellular automaton/neural network classifier for multi-valued patterns and its VLSI implementation. Integration 20(2): 211-237 (1996)

j10

Ioannis Andreadis, Ioannis Karafyllidis, Panagiotis Tzionas, Adonios Thanailakis, Phillipos Tsalides: A new hardware module for automated visual inspection based on a cellular automaton architecture. Journal of Intelligent and Robotic Systems 16(1): 89-102 (1996)

Ioannis Karafyllidis, Ioannis Andreadis, Panagiotis Tzionas, Phillipos G. Tsalides, Adonios Thanailakis: A cellular automaton for the determination of the mean velocity of moving objects and its VLSI implementation. Pattern Recognition 29(4): 689-699 (1996)

1995

Panagiotis Tzionas, Phillipos G. Tsalides, Adonios Thanailakis: A Parallel Skeletonization Algorithm Based on Two-Dimensional Cellular Automata and its VLSI Implementation. Real-Time Imaging 1(2): 105-117 (1995)

1994

E. D. Adamides, Phillipos G. Tsalides, Adonios Thanailakis: Bit-serial VLSI sorter with high reliability specifications. Microprocessing and Microprogramming 40(8): 523-536 (1994)

Panagiotis Tzionas, Panagiotis G. Tsalides, Adonios Thanailakis: A new, cellular automaton-based, nearest neighbor pattern classifier and its VLSI implementation. IEEE Trans. VLSI Syst. 2(3): 343-353 (1994)

1993

Panagiotis Tzionas, Phillipos Tsalides, Antonios Thanailakis: 2-Dimensional minimum cost path planning using a cellular automaton architecture. Integration 16(2): 179-194 (1993)

1992

E. D. Adamides, Phillipos Tsalides, Adonios Thanailakis: Hierarchical Cellular Automata structures. Parallel Computing 18(5): 517-524 (1992)

1989

E. D. Adamides, Phillipos Tsalides, Adonios Thanailakis: Synchronization of D. Parkinsonasynchronous concurrent processes using cellular automata. Parallel Computing 11(2): 163-169 (1989)

1986

Howard C. Card, Adonios Thanailakis, Werner Pries, Robert D. McLeod: Analysis of Bounded Linear Cellular Automata Based on a Method of Image Charges. J. Comput. Syst. Sci. 33(3): 473-480 (1986)

Werner Pries, Adonios Thanailakis, Howard C. Card: Group Properties of Cellular Automata and VLSI Applications. IEEE Trans. Computers 35(12): 1013-1024 (1986)

1	E. D. Adamides	[j7] [j4] [j3]
2	Ioannis Andreadis	[j10] [j9]
3	Antonios Argyriou	[j25] [j16] [c6] [c3]
4	David Atienza (David Atienza Alonso)	[j28] [j27] [c33] [c19] [c14]
5	Christos Baloukas	[j27] [c19]
6	Alexandros Bartzas	[j28] [c33]
7	Spyros Blionas	[c16] [c12] [c10] [c7]
8	Erik Brockmeyer	[i1] [j26] [c26] [c21] [c15]
9	Howard C. Card	[j2] [j1]
10	Francky Catthoor	[j28] [i1] [j27] [j26] [c33] [c26] [c21] [c19] [c15] [c14]
11	M. M. Dasigenis	[c4]
12	Minas Dasygenis	[j32] [i1] [j26] [j25] [c26] [c22] [c21] [c20] [c15] [j16] [c6] [c3]
13	Chrissavgi Dre	[c2]
14	Bart Durinck	[i1] [j26] [c26] [c15]
15	J. M. Fernandez	[c5]
16	Constantinos E. Goutis (Costas E. Goutis)	[j14] [c6] [c3] [c2]
17	A. Ioannidis	[j12]
18	Vasilios Kalenteridis	[j22] [c27] [c17]
19	Grigorios Kalivas (Grigorios A. Kalivas)	[c2]
20	Ioannis Karafyllidis	[j31] [j24] [j23] [j19] [j18] [j17] [j15] [c1] [j12] [j10] [j9]
21	C. Katis	[c2]
22	Marios Kesoulis	[j30] [c12] [c8]
23	Christos S. Koukourlis	[j30] [c12] [c8]
24	George Koutroumpezis	[j29] [j22] [c27] [c25] [c23] [c18] [c17] [c7]
25	Nikolas Kroupis	[j25] [c22] [c20] [j16] [c6]
26	Stylianos Mamagkakis (Stelios Mamagkakis)	[j28] [c34] [j27] [c33] [c19] [c14]
27	Vasilios A. Mardiris	[j31] [j18]
28	K. Markou	[c22]
29	Kostas Masselos (Konstantinos Masselos)	[c16] [c10] [c7]
30	Robert D. McLeod	[j2]
31	Jose Manuel Mendias (José M. Mendías)	[c19] [c14]
32	E. G. Metaxakis	[c2]
33	K. Mitroglou	[j32]
34	Ch. Mizas	[j31] [j18]
35	Alexandros Mpartzas	[c14]
36	Spiridon Nikolaidis	[j22] [c27] [c17] [c9]
37	Ilias Pappas	[j22] [c27] [c17]
38	Vasilis F. Pavlidis	[c11]
39	M. Perakis	[c2]
40	Konstantinos Potamianos	[c16] [c10]
41	Georgios Pouiklis	[j28] [c33] [c14]
42	Haroula Pournara	[j22] [c27] [c17]
43	Werner Pries	[j2] [j1]
44	V. Raptis	[j24]
45	K. Sgouropoulos	[c11]
46	D. Siomos	[j21]
47	Kostas Siozios (K. Siozios)	[j34] [j33] [c34] [c32] [c31] [c30] [c29] [c28] [j22] [c27] [c25] [c24] [c23] [c18] [c17] [c13] [c10] [c9]
48	Georgios Ch. Sirakoulis	[j31] [j24] [j23] [j18] [j17] [j15]
49	Stilianos Siskos (Stylianos Siskos, Stelios Siskos)	[j22] [c27] [c17] [c9]
50	Dimitrios Soudris (D. J. Soudris)	[j34] [j33] [j32] [j30] [j29] [j28] [c34] [i1] [j27] [j26] [j25] [c33] [c32] [c31] [c30] [c29] [c28] [j22] [j21] [j20] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [j16] [c13] [c12] [c11] [c10] [c9] [c8] [j14] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
51	Thanos Stouraitis	[c2] [c1]
52	Konstantinos Tatas (K. Tatas)	[j29] [j25] [c32] [c31] [j22] [j21] [j20] [c27] [c25] [c23] [c18] [c17] [c16] [j16] [c13] [c11] [c10] [c9] [c7] [c6] [c3]
53	Evaggelia Theochari	[c16]
54	George Theodoridis	[j14]
55	Spyros Theoharis (S. Theoharis)	[j14]
56	I. Thoidis	[c5] [c1]
57	Panagiotis G. Tsalides	[j6]
58	Phillipos Tsalides	[j24] [j18] [j12] [j11] [j10] [j5] [j4] [j3]
59	Phillipos G. Tsalides	[j13] [j9] [j8] [j7]
60	Ioannis Tsimperidis	[j19]
61	A. E. Tzimas	[c2]
62	Panagiotis Tzionas	[j13] [j11] [j10] [j9] [j8] [j6] [j5]
63	S. K. Vasilopoulou	[c4]
64	Nikolaos Vassiliadis	[j22] [c27] [c9]
65	Nikolaos D. Zervas	[j25] [c6] [c3]

Adonios Thanailakis

Coauthor Index