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Russell Tessier
2010 – today
- 2013
[j23]Jérémie Crenne, Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Deepak Unnikrishnan: Configurable memory security in embedded systems. ACM Trans. Embedded Comput. Syst. 12(3): 71 (2013)- [c49]Harikrishnan Chandrikakutty, Deepak Unnikrishnan, Russell Tessier, Tilman Wolf: High-performance hardware monitors to protect network processors from data plane attacks. DAC 2013: 80
- [c48]Jia Zhao, Shiting (Justin) Lu, Wayne Burleson, Russell Tessier: Run-time probabilistic detection of miscalibrated thermal sensors in many-core systems. DATE 2013: 1395-1398
- [c47]Daniel Gomez-Prado, Maciej J. Ciesielski, Russell Tessier: FPGA latency optimization using system-level transformations and DFG restructuring. DATE 2013: 1553-1558
- 2012
- [c46]Jia Zhao, Russell Tessier, Wayne Burleson: Distributed sensor data processing for many-cores. ACM Great Lakes Symposium on VLSI 2012: 159-164
- [c45]Y. Sinan Hanay, Wei Li, Russell Tessier, Tilman Wolf: Saving energy and improving TCP throughput with rate adaptation in Ethernet. ICC 2012: 1249-1254
- [c44]Shiting (Justin) Lu, Russell Tessier, Wayne Burleson: Collaborative calibration of on-chip thermal sensors using performance counters. ICCAD 2012: 15-22
- 2011
- [j22]Dong Yin, Deepak Unnikrishnan, Yong Liao, Lixin Gao, Russell Tessier: Customizing virtual networks with partial FPGA reconfiguration. Computer Communication Review 41(1): 125-132 (2011)
- [j21]Tilman Wolf, Russell Tessier, Gayatri Prabhu: Securing the data path of next-generation router systems. Computer Communications 34(4): 598-606 (2011)
- [j20]Jia Zhao, Sailaja Madduri, Ramakrishna Vadlamani, Wayne Burleson, Russell Tessier: A Dedicated Monitoring Infrastructure for Multicore Processors. IEEE Trans. VLSI Syst. 19(6): 1011-1022 (2011)
- [c43]Vishwas Vijayendra, Paul Siqueira, Harikrishnan Chandrikakutty, Akilesh Krishnamurthy, Russell Tessier: Real-time estimates of differential signal phase for spaceborne systems using FPGAs. AHS 2011: 121-128
- [c42]Deepak Unnikrishnan, Justin Lu, Lixin Gao, Russell Tessier: ReClick - A Modular Dataplane Design Framework for FPGA-Based Network Virtualization. ANCS 2011: 145-155
- [c41]Emmanuel Seguin, Russell Tessier, Eric J. Knapp, Robert W. Jackson: A Dynamically-Reconfigurable Phased Array Radar Processing System. FPL 2011: 258-263
- [c40]Jérémie Crenne, Pascal Cotret, Guy Gogniat, Russell Tessier, Jean-Philippe Diguet: Efficient key-dependent message authentication in reconfigurable hardware. FPT 2011: 1-6
- [c39]Ben Bovee, Mohammad Nekoui, Hossein Pishro-Nik, Russell Tessier: Evaluation of the Universal Geocast Scheme for VANETs. VTC Fall 2011: 1-5
- [e3]Russell Tessier (Ed.): 2011 International Conference on Field-Programmable Technology, FPT 2011, New Delhi, India, December 12-14, 2011. IEEE 2011, ISBN 978-1-4577-1741-3
- 2010
- [c38]Ramakrishna Vadlamani, Jia Zhao, Wayne P. Burleson, Russell Tessier: Multicore soft error rate stabilization using adaptive dual modular redundancy. DATE 2010: 27-32
- [c37]Russell Tessier, Salma Mirza, J. Blair Perot: Reconfigurable Sparse Matrix-Vector Multiplication on FPGAs. ERSA 2010: 77-83
- [c36]Deepak Unnikrishnan, Ramakrishna Vadlamani, Yong Liao, Abhishek Dwaraki, Jérémie Crenne, Lixin Gao, Russell Tessier: Scalable network virtualization using FPGAs. FPGA 2010: 219-228
- [c35]Jia Zhao, Basab Datta, Wayne P. Burleson, Russell Tessier: Thermal-aware voltage droop compensation for multi-core architectures. ACM Great Lakes Symposium on VLSI 2010: 335-340
- [e2]Ron Sass, Russell Tessier (Eds.): 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2010, Charlotte, North Carolina, USA, 2-4 May 2010. IEEE Computer Society 2010, ISBN 978-0-7695-4056-6
2000 – 2009
- 2009
- [j19]Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Eduardo Wanderley Netto, Russell Tessier, Wayne P. Burleson: A security approach for off-chip memory in embedded microprocessor systems. Microprocessors and Microsystems - Embedded Hardware Design 33(1): 37-45 (2009)
- [j18]Weifeng Xu, Russell Tessier: Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors. TACO 6(3) (2009)
- [c34]Sailaja Madduri, Ramakrishna Vadlamani, Wayne Burleson, Russell Tessier: A monitor interconnect and support subsystem for multicore processors. DATE 2009: 761-766
- [c33]Deepak Unnikrishnan, Jia Zhao, Russell Tessier: Application Specific Customization and Scalability of Soft Multiprocessors. FCCM 2009: 123-130
- [c32]Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger: CMOS vs Nano: comrades or rivals? FPGA 2009: 121-122
- [c31]Tilman Wolf, Russell Tessier: Design of a Secure Router System for Next-Generation Networks. NSS 2009: 52-59
- [c30]Kevin Andryc, Russell Tessier, Patrick Kelly: An Interactive Approach to Timing Accurate PCI-X Simulation. IEEE International Workshop on Rapid System Prototyping 2009: 181-187
- 2008
- [c29]Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Deepak Unnikrishnan, Kris Gaj: Memory security management for reconfigurable embedded systems. FPT 2008: 153-160
- 2007
- [j17]Ian Kuon, Russell Tessier, Jonathan Rose: FPGA Architecture: Survey and Challenges. Foundations and Trends in Electronic Design Automation 2(2): 135-253 (2007)
- [j16]Russell Tessier, Vaughn Betz, David Neto, Aaron Egier, Thiagaraja Gopalsamy: Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 278-290 (2007)
- [c28]Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Wayne Burleson: High-efficiency protection solution for off-chip memory in embedded systems. ERSA 2007: 117-123
- [c27]Thomas Eisenbarth, Tim Güneysu, Christof Paar, Ahmad-Reza Sadeghi, Marko Wolf, Russell Tessier: Establishing Chain of Trust in Reconfigurable Hardware. FCCM 2007: 289-290
- [c26]Kevin Oo Tinmaung, David Howland, Russell Tessier: Power-aware FPGA logic synthesis using binary decision diagrams. FPGA 2007: 148-155
- [c25]Weifeng Xu, Russell Tessier: Tetris: a new register pressure control technique for VLIW processors. LCTES 2007: 113-122
- [c24]Romain Vaslin, Guy Gogniat, Eduardo Wanderley Netto, Russell Tessier, Wayne P. Burleson: Low latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip Memory. ReCoSoC 2007: 146-153
- 2006
- [j15]Miriam Leeser, Scott Hauck, Russell Tessier: Field-Programmable Gate Arrays in Embedded Systems. EURASIP J. Emb. Sys. 2006 (2006)
- [j14]Premachandran R. Menon, Weifeng Xu, Russell Tessier: Design-specific path delay testing in lookup-table-based FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 867-877 (2006)
- [c23]Lilian Atieno, Jonathan Allen, Dennis Goeckel, Russell Tessier: An adaptive Reed-Solomon errors-and-erasures decoder. FPGA 2006: 150-158
- [c22]Russell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy: Power-aware RAM mapping for FPGA embedded memory blocks. FPGA 2006: 189-198
- 2005
- [j13]Russell Tessier, Sriram Swaminathan, Ramaswamy Ramaswamy, Dennis Goeckel, Wayne P. Burleson: A reconfigurable, power-efficient adaptive Viterbi decoder. IEEE Trans. VLSI Syst. 13(4): 484-488 (2005)
- [j12]Russell Tessier, David Jasinski, Atul Maheshwari, Aiyappan Natarajan, Weifeng Xu, Wayne P. Burleson: An energy-aware active smart card. IEEE Trans. VLSI Syst. 13(10): 1190-1199 (2005)
- [c21]Francesc Junyent, Venkatachalam Chandrasekar, David J. McLaughlin, Stephen J. Frasier, Edin Insanic, Razi Ahmed, Nitin Bharadwaj, Eric J. Knapp, Luko Krnan, Russell Tessier: Salient features of radar nodes of the first generation NetRad System. IGARSS 2005: 4
- 2004
- [j11]Atul Maheshwari, Wayne Burleson, Russell Tessier: Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits. IEEE Trans. VLSI Syst. 12(3): 299-311 (2004)
- [j10]Jian Liang, Andrew Laffely, S. Srinivasan, Russell Tessier: An architecture and compiler for scalable on-chip communication. IEEE Trans. VLSI Syst. 12(7): 711-726 (2004)
- [j9]Roger Woods, Russell Tessier: Guest Editorial: Field Programmable Logic. VLSI Signal Processing 36(1): 5-6 (2004)
- [j8]Prashant Jain, Andrew Laffely, Wayne Burleson, Russell Tessier, Dennis Goeckel: Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations. VLSI Signal Processing 36(1): 27-40 (2004)
- [c20]Jian Liang, Russell Tessier, Dennis Goeckel: A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder. FCCM 2004: 91-100
- [e1]Russell Tessier, Herman Schmit (Eds.): Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004. ACM 2004, ISBN 1-58113-829-6
- 2003
- [j7]Srini Krishnamoorthy, Russell Tessier: Technology mapping algorithms for hybrid FPGAs containing lookup tables and PLAs. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 545-559 (2003)
- [c19]Weifeng Xu, Ramshankar Ramanarayanan, Russell Tessier: Adaptive Fault Recovery for Networked Reconfigurable Systems. FCCM 2003: 143-
- [c18]Jian Liang, Russell Tessier, Oskar Mencer: Floating Point Unit Generation and Evaluation for FPGAs. FCCM 2003: 185-194
- [c17]Aiyappan Natarajan, David Jasinski, Wayne Burleson, Russell Tessier: A hybrid adiabatic content addressable memory for ultra low-power applications. ACM Great Lakes Symposium on VLSI 2003: 72-75
- [c16]Andrew Laffely, Jian Liang, Russell Tessier, Wayne Burleson: Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores. ICIP (3) 2003: 105-108
- 2002
- [j6]Murali Kudlugi, Russell Tessier: Static scheduling of multidomain circuits for fast functional verification. IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1253-1268 (2002)
- [j5]Ian G. Harris, Russell Tessier: Testing and diagnosis of interconnect faults in cluster-based FPGA architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1337-1343 (2002)
- [j4]Russell Tessier: Fast placement approaches for FPGAs. ACM Trans. Design Autom. Electr. Syst. 7(2): 284-305 (2002)
- [j3]Navin Vemuri, Priyank Kalla, Russell Tessier: BDD-based logic synthesis for LUT-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 7(4): 501-525 (2002)
- [c15]Sriram Swaminathan, Russell Tessier, Dennis Goeckel, Wayne Burleson: A dynamically reconfigurable adaptive viterbi decoder. FPGA 2002: 227-236
- [c14]Ramaswamy Ramaswamy, Russell Tessier: The Integration of SystemC and Hardware-Assisted Verification. FPL 2002: 1007-1016
- [c13]Atul Maheshwari, Wayne Burleson, Russell Tessier: Trading off Reliability and Power-Consumption in Ultra-low Power Systems. ISQED 2002: 361-366
- 2001
- [j2]Russell Tessier, Wayne Burleson: Reconfigurable Computing for Digital Signal Processing: A Survey. VLSI Signal Processing 28(1-2): 7-27 (2001)
- [c12]Murali Kudlugi, Charles Selvidge, Russell Tessier: Static Scheduling of Multiple Asynchronous Domains For Functional Verification. DAC 2001: 647-652
- [c11]Murali Kudlugi, Charles Selvidge, Russell Tessier: Static Scheduling of Multi-Domain Memories For Functional Verification. ICCAD 2001: 2-9
- [c10]Ian G. Harris, Premachandran R. Menon, Russell Tessier: BIST-based delay path testing in FPGA architectures. ITC 2001: 932-938
- 2000
- [c9]Jian Liang, Sriram Swaminathan, Russell Tessier: aSOC: A Scalable, Single-Chip Communications Architecture. IEEE PACT 2000: 37-46
- [c8]Ian G. Harris, Russell Tessier: Interconnect testing in cluster-based FPGA architectures. DAC 2000: 49-54
- [c7]Vijay Lakamraju, Russell Tessier: Tolerating operational faults in cluster-based FPGAs. FPGA 2000: 187-194
- [c6]Srini Krishnamoorthy, Sriram Swaminathan, Russell Tessier: Area-Optimized Technology Mapping for Hybrid FPGAs. FPL 2000: 181-190
- [c5]Russell Tessier, Heather Giza: Balancing Logic Utilization and Area Efficiency in FPGAs. FPL 2000: 535-544
- [c4]Ian G. Harris, Russell Tessier: Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures. ICCAD 2000: 472-475
1990 – 1999
- 1999
- [c3]
- [c2]Russell Tessier: Incremental Compilation for Logic Emulation. IEEE International Workshop on Rapid System Prototyping 1999: 236-241
- 1997
- [j1]Jonathan Babb, Russell Tessier, Matthew Dahl, Silvina Hanono, David M. Hoki, Anant Agarwal: Logic emulation with virtual wires. IEEE Trans. on CAD of Integrated Circuits and Systems 16(6): 609-626 (1997)
- 1993
- [c1]Steve Ward, Karim Abdalla, Rajeev Dujari, Michael Fetterman, Frank Honoré, Ricardo Jenez, Philippe Laffont, Kenneth Mackenzie, Chris Metcalf, Milan Minsky, John Nguyen, John Pezaris, Gill A. Pratt, Russell Tessier: The NuMesh: A Modular, Scalable Communications Substrate. International Conference on Supercomputing 1993: 230-239
Coauthor Index
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last updated on 2013-05-29 01:54 CEST by the dblp team