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Jürgen Teich
Author information
- University of Erlangen-Nuremberg
2010 – today
- 2013
[j51]Joachim Falk, Christian Zebelein, Christian Haubelt, Jürgen Teich: A rule-based quasi-static scheduling approach for static islands in dynamic dataflow graphs. ACM Trans. Embedded Comput. Syst. 12(3): 74 (2013)- [j50]Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker: Virtual networks - distributed communication resource management. TRETS 6(2): 8 (2013)
- [c264]Yang Xu, Bo Wang, Rafael Rosales, Ralph Hasholzner, Jürgen Teich: On Confident Task-Accurate Performance Estimation. ARCS 2013: 25-37
- [c263]Tobias Ziermann, Zoran Salcic, Jürgen Teich: HW/SW Tradeoffs for Dynamic Message Scheduling in Controller Area Network (CAN). ARCS 2013: 159-170
- [c262]Jürgen Teich, Alexandru Tanase, Frank Hannig: Symbolic parallelization of loop programs for massively parallel processor arrays. ASAP 2013: 1-9
- [c261]Srinivas Boppu, Frank Hannig, Jürgen Teich: Loop program mapping and compact code generation for programmable hardware accelerators. ASAP 2013: 10-17
- [c260]Frank Hannig, Moritz Schmid, Vahid Lari, Srinivas Boppu, Jürgen Teich: System integration of tightly-coupled processor arrays using reconfigurable buffer structures. Conf. Computing Frontiers 2013: 2
- [c259]Yang Xu, Bo Wang, Ralph Hasholzner, Rafael Rosales, Jürgen Teich: On robust task-accurate performance estimation. DAC 2013: 171
- [c258]Stefan Wildermann, Tobias Ziermann, Jürgen Teich: Game-theoretic analysis of decentralized core allocation schemes on many-core systems. DATE 2013: 1498-1503
- [c257]Hananeh Aliee, Michael Glaß, Felix Reimann, Jürgen Teich: Automatic success tree-based reliability analysis for the consideration of transient and permanent faults. DATE 2013: 1621-1626
- [c256]Christopher Dennl, Daniel Ziener, Jürgen Teich: Acceleration of SQL Restrictions and Aggregations through FPGA-Based Dynamic Partial Reconfiguration. FCCM 2013: 25-28
- [c255]Christian Zebelein, Christian Haubelt, Joachim Falk, Jürgen Teich: Model-Based Representation of Schedules for Dataflow Graphs. MBMV 2013: 105-115
- [c254]Sebastian Graf, Michael Glaß, Jürgen Teich: Investigating the Impact of Energy-Efficient Ethernet on Automotive Applications via High-level Modeling. MBMV 2013: 117-128
- [i8]Jürgen Teich, Wolfgang Schröder-Preikschat, Andreas Herkersdorf: Invasive Computing - Common Terms and Granularity of Invasion. CoRR abs/1304.6067 (2013)
- 2012
- [j49]Tobias Ziermann, Stefan Wildermann, Nina Mühleis, Jürgen Teich: Distributed self-organizing bandwidth allocation for priority-based bus communication. Concurrency and Computation: Practice and Experience 24(16): 1903-1917 (2012)
- [j48]Stefan Wildermann, Josef Angermeier, Eugen Sibirko, Jürgen Teich: Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures. Int. J. Reconfig. Comp. 2012 (2012)
- [j47]Jürgen Teich: Hardware/Software Codesign: The Past, the Present, and Predicting the Future. Proceedings of the IEEE 100(Centennial-Issue): 1411-1430 (2012)
- [j46]Jens Gladigau, Christian Haubelt, Jürgen Teich: Model-Based Virtual Prototype Acceleration. IEEE Trans. on CAD of Integrated Circuits and Systems 31(10): 1572-1585 (2012)
- [j45]Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Moritz Schmid, Jürgen Teich: Hierarchical power management for adaptive tightly-coupled processor arrays. ACM Trans. Design Autom. Electr. Syst. 18(1): 2 (2012)
- [j44]Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich: Dynamic Defragmentation of Reconfigurable Devices. TRETS 5(2): 8 (2012)
- [c253]Jürgen Teich: Keynote address II: Exploiting dynamic hardware reconfigurability for efficiency, performance, and reliability. AHS 2012
- [c252]Yang Xu, Rafael Rosales, Bo Wang, Martin Streubühr, Ralph Hasholzner, Christian Haubelt, Jürgen Teich: A Very Fast and Quasi-accurate Power-State-Based System-Level Power Modeling Methodology. ARCS 2012: 37-49
- [c251]Richard Membarth, Jan-Hugo Lupp, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert: Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging. ARCS 2012: 147-159
- [c250]Dirk Koch, Jim Torresen, Christian Beckhoff, Daniel Ziener, Christopher Dennl, Volker Breuer, Jürgen Teich, Michael Feilen, Walter Stechele: Partial Reconfiguration on FPGAs in Practice - Tools and Applications. ARCS Workshops 2012: 297-319
- [c249]Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Jürgen Teich: Design of Low Power On-chip Processor Arrays. ASAP 2012: 165-168
- [c248]Sascha Roloff, Frank Hannig, Jürgen Teich: Approximate time functional simulation of resource-aware programming concepts for heterogeneous MPSoCs. ASP-DAC 2012: 187-192
- [c247]Martin Lukasiewycz, Michael Glaß, Jürgen Teich, Paul Milbredt: FlexRay Static Segment Scheduling. Advances in Real-Time Systems 2012: 323-339
- [c246]Michael Eberl, Michael Glaß, Jürgen Teich, Ulrich Abelein: Considering diagnosis functionality during automatic system-level design of automotive networks. DAC 2012: 205-213
- [c245]Shravan Muddasani, Srinivas Boppu, Frank Hannig, Boris Kuzmin, Vahid Lari, Jürgen Teich: A prototype of an invasive tightly-coupled processor array. DASIP 2012: 1-2
- [c244]Paul Milbredt, Michael Glaß, Martin Lukasiewycz, Andreas Steininger, Jürgen Teich: Designing FlexRay-based automotive architectures: A holistic OEM approach. DATE 2012: 276-279
- [c243]Yang Xu, Bing Li, Ralph Hasholzner, Bernhard Rohfleisch, Christian Haubelt, Jürgen Teich: Variation-aware leakage power model extraction for system-level hierarchical power analysis. DATE 2012: 346-351
- [c242]Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert: Mastering Software Variant Explosion for GPU Accelerators. Euro-Par Workshops 2012: 123-132
- [c241]Christopher Dennl, Daniel Ziener, Jürgen Teich: On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library. FCCM 2012: 45-52
- [c240]Moritz Schmid, Frank Hannig, Jürgen Teich: Power Management Strategies for Serial RapidIO Endpoints in FPGAs. FCCM 2012: 101-108
- [c239]Jürgen Teich, Andreas Weichslgartner, Benjamin Oechslein, Wolfgang Schröder-Preikschat: Invasive computing - Concepts and overheads. FDL 2012: 217-224
- [c238]Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker: Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS. IPDPS Workshops 2012: 234-241
- [c237]Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert: Generating Device-specific GPU Code for Local Operators in Medical Imaging. IPDPS 2012: 569-581
- [c236]Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert: Automatic Optimization of In-Flight Memory Transactions for GPU Accelerators Based on a Domain-Specific Language for Medical Imaging. ISPDC 2012: 211-218
- [c235]Sebastian Graf, Michael Glaß, Jürgen Teich: Unreliable Data Transmissions und Limited Hardware Communication Buffers in Automotive E/E Virtual Prototypes. MBMV 2012: 13-24
- [c234]Christian Zebelein, Christian Haubelt, Joachim Falk, Jürgen Teich: Exploiting Model-Knowledge in High-Level Synthesis. MBMV 2012: 181-191
- [c233]Liyuan Zhang, Michael Glaß, Martin Streubühr, Jürgen Teich, Andreas von Schwerin, Kai Liu: Actor-oriented Modeling und Simulation of Cut-through Communication in Network Controllers. MBMV 2012: 193-204
- [c232]Tobias Ziermann, Alexander Butiu, Jürgen Teich, Daniel Ziener: FPGA-based testbed for timing behavior evaluation of the Controller Area Network (CAN). ReConFig 2012: 1-6
- [c231]Michael Glaß, Heng Yu, Felix Reimann, Jürgen Teich: Cross-Level Compositional Reliability Analysis for Embedded Systems. SAFECOMP 2012: 111-124
- [c230]Rainer Kiesel, Martin Streubühr, Christian Haubelt, Anestis Terzis, Jürgen Teich: Virtual prototyping for efficient multi-core ECU development of driver assistance systems. ICSAMOS 2012: 33-40
- [c229]Michael Glaß, Jürgen Teich, Liyuan Zhang: A co-simulation approach for system-level analysis of embedded control systems. ICSAMOS 2012: 355-362
- [c228]Richard Membarth, Frank Hannig, Jürgen Teich, Harald Köstler: Towards Domain-Specific Computing for Stencil Codes in HPC. SC Companion 2012: 1133-1138
- 2011
- [b4]Joachim Keinert, Jürgen Teich: Design of Image Processing Embedded Systems Using Multidimensional Data Flow. Embedded Systems, Springer 2011, ISBN 978-1-4419-7181-4
- [j43]Dmitrij Kissler, D. Gran, Zoran Salcic, Frank Hannig, Jürgen Teich: Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays. Embedded Systems Letters 3(2): 58-61 (2011)
- [j42]Dmitrij Kissler, Frank Hannig, Jürgen Teich: Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays. J. Low Power Electronics 7(1): 29-40 (2011)
- [j41]Nina Mühleis, Michael Glaß, Liyuan Zhang, Jürgen Teich: A co-simulation approach for control performance analysis during design space exploration of cyber-physical systems. SIGBED Review 8(2): 23-26 (2011)
- [c227]Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert: Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image Registration. ARCS 2011: 62-73
- [c226]Andreas Kern, Dominik Reinhard, Thilo Streichert, Jürgen Teich: Gateway Strategies for Embedding of Automotive CAN-Frames into Ethernet-Packets and Vice Versa. ARCS 2011: 259-270
- [c225]Vahid Lari, Andriy Narovlyanskyy, Frank Hannig, Jürgen Teich: Decentralized dynamic resource management support for massively parallel processor arrays. ASAP 2011: 87-94
- [c224]Tobias Ziermann, Zoran Salcic, Jürgen Teich: Self-organized Message Scheduling for Asynchronous Distributed Embedded Systems. ATC 2011: 132-148
- [c223]Jörg Henkel, Lars Bauer, Joachim Becker, Oliver Bringmann, Uwe Brinkschulte, Samarjit Chakraborty, Michael Engel, Rolf Ernst, Hermann Härtig, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel Lohmann, Peter Marwedel, Marco Platzner, Wolfgang Rosenstiel, Ulf Schlichtmann, Olaf Spinczyk, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Hans-Joachim Wunderlich: Design and architectures for dependable embedded systems. CODES+ISSS 2011: 69-78
- [c222]Peter Marwedel, Jürgen Teich, Georgia Kouveli, Iuliana Bacivarov, Lothar Thiele, Soonhoi Ha, Chanhee Lee, Qiang Xu, Lin Huang: Mapping of applications to MPSoCs. CODES+ISSS 2011: 109-118
- [c221]Stefan Wildermann, Felix Reimann, Daniel Ziener, Jürgen Teich: Symbolic design space exploration for multi-mode reconfigurable systems. CODES+ISSS 2011: 129-138
- [c220]Felix Reimann, Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich: Symbolic system synthesis in the presence of stringent real-time constraints. DAC 2011: 393-398
- [c219]Andreas Kern, Helge Zinner, Thilo Streichert, Josef Nöbauer, Jürgen Teich: Accuracy of ethernet AVB time synchronization under varying temperature conditions for automotive networks. DAC 2011: 597-602
- [c218]Andreas Kern, Thilo Streichert, Jürgen Teich: An automated data structure migration concept - From CAN to Ethernet/IP in automotive embedded systems (CANoverIP). DATE 2011: 112-117
- [c217]Tobias Ziermann, Jürgen Teich, Zoran Salcic: DynOAA - Dynamic offset adaptation algorithm for improving response times of CAN systems. DATE 2011: 269-272
- [c216]Joachim Falk, Christian Zebelein, Christian Haubelt, Jürgen Teich: A rule-based static dataflow clustering algorithm for efficient embedded software synthesis. DATE 2011: 521-526
- [c215]Martin Streubühr, Rafael Rosales, Ralph Hasholzner, Christian Haubelt, Jürgen Teich: ESL power and performance estimation for heterogeneous MPSOCS using SystemC. FDL 2011: 1-8
- [c214]Josef Angermeier, Daniel Ziener, Michael Glaß, Jürgen Teich: Stress-Aware Module Placement on Reconfigurable Devices. FPL 2011: 277-281
- [c213]Stefan Wildermann, Jürgen Teich, Daniel Ziener: Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCs. FPL 2011: 429-434
- [c212]Josef Angermeier, Daniel Ziener, Michael Glaß, Jürgen Teich: Runtime stress-aware replica placement on reconfigurable devices under safety constraints. FPT 2011: 1-6
- [c211]Stefan Wildermann, Felix Reimann, Jürgen Teich, Zoran Salcic: Operational mode exploration for reconfigurable systems with multiple applications. FPT 2011: 1-8
- [c210]Tobias Ziermann, Bernhard Schmidt, Moritz Mühlenthaler, Daniel Ziener, Josef Angermeier, Jürgen Teich: An FPGA implementation of a threat-based strategy for Connect6. FPT 2011: 1-4
- [c209]Martin Lukasiewycz, Michael Glaß, Felix Reimann, Jürgen Teich: Opt4J: a modular framework for meta-heuristic optimization. GECCO 2011: 1723-1730
- [c208]Josef Angermeier, Eugen Sibirko, Rolf Wanka, Jürgen Teich: Bitonic Sorting on Dynamically Reconfigurable Architectures. IPDPS Workshops 2011: 314-317
- [c207]Vahid Lari, Frank Hannig, Jürgen Teich: Distributed Resource Reservation in Massively Parallel Processor Arrays. IPDPS Workshops 2011: 318-321
- [c206]Georgia Kouveli, Frank Hannig, Jan-Hugo Lupp, Jürgen Teich: Towards Resource Aware Programming on Intel's Single-Chip Cloud Computer Processor. MARC Symposium 2011: 111-114
- [c205]Andreas Weichslgartner, Stefan Wildermann, Jürgen Teich: Dynamic decentralized mapping of tree-structured applications on NoC architectures. NOCS 2011: 201-208
- [c204]Srinivas Boppu, Frank Hannig, Jürgen Teich, Roberto Perez-Andrade: Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays. ReConFig 2011: 392-397
- [c203]Philipp Kutzer, Jens Gladigau, Christian Haubelt, Jürgen Teich: Automatic generation of system-level virtual prototypes from streaming application models. International Symposium on Rapid System Prototyping 2011: 128-134
- [c202]Rainer Kiesel, Martin Streubühr, Christian Haubelt, Otto Löhlein, Jürgen Teich: Calibration and validation of software performance models for pedestrian detection systems. ICSAMOS 2011: 182-189
- [c201]Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert: Frameworks for GPU Accelerators: A comprehensive evaluation using 2D/3D image registration. SASP 2011: 78-81
- [c200]Frank Hannig, Sascha Roloff, Gregor Snelting, Jürgen Teich, Andreas Zwinkau: Resource-aware programming and simulation of MPSoC architectures through extension of X10. SCOPES 2011: 48-55
- [c199]Andreas Kern, Hongyan Zhang, Thilo Streichert, Jürgen Teich: Testing switched Ethernet networks in automotive embedded systems. SIES 2011: 150-155
- [p5]Tobias Ziermann, Stefan Wildermann, Jürgen Teich: OrganicBus: Organic Self-organising Bus-Based Communication Systems. Organic Computing 2011: 489-501
- [p4]Jürgen Teich, Jörg Henkel, Andreas Herkersdorf, Doris Schmitt-Landsiedel, Wolfgang Schröder-Preikschat, Gregor Snelting: Invasive Computing: An Overview. Multiprocessor System-on-Chip 2011: 241-268
- 2010
- [b3]Christian Haubelt, Jürgen Teich: Digitale Hardware/Software-Systeme: Spezifikation und Verifikation. eXamen.press, Springer 2010, ISBN 978-3-642-05355-9
- [j40]Udo Kebschull, Marco Platzner, Jürgen Teich: Selected papers from the 18th International Conference on Field Programmable Logic and Applications (FPL 2008) [Editorial]. IET Computers & Digital Techniques 4(3): 157-158 (2010)
- [j39]Joachim Falk, Christian Zebelein, Joachim Keinert, Christian Haubelt, Jürgen Teich, Shuvra S. Bhattacharyya: Analysis of SystemC actor networks for efficient synthesis. ACM Trans. Embedded Comput. Syst. 10(2): 18 (2010)
- [c198]Stefan Wildermann, Andreas Oetken, Jürgen Teich, Zoran A. Salcic: Self-organizing Computer Vision for Robust Object Tracking in Smart Cameras. ATC 2010: 1-16
- [c197]Felix Reimann, Michael Glaß, Christian Haubelt, Michael Eberl, Jürgen Teich: Improving platform-based system synthesis by satisfiability modulo theories solving. CODES+ISSS 2010: 135-144
- [c196]Michael Glaß, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich: Towards scalable system-level reliability analysis. DAC 2010: 234-239
- [c195]Matthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jürgen Teich: A rapid prototyping system for error-resilient multi-processor systems-on-chip. DATE 2010: 375-380
- [c194]Christian Zebelein, Joachim Falk, Christian Haubelt, Jürgen Teich, Rainer Dorsch: Efficient High-Level modeling in the networking domain. DATE 2010: 1189-1194
- [c193]Martin Lukasiewycz, Michael Glaß, Jürgen Teich: Robust design of embedded systems. DATE 2010: 1578-1583
- [c192]Samarjit Chakraborty, S. Ramesh, Jürgen Teich: Model-based analysis, synthesis and testing of automotive hardware/software architectures. EMSOFT 2010: 299-300
- [c191]Richard Membarth, Anton Lokhmotov, Jürgen Teich: Generating GPU Code from a High-Level Representation for Image Processing Kernels. Euro-Par Workshops (1) 2010: 270-280
- [c190]Joon Edward Sim, Weng-Fai Wong, Gregor Walla, Tobias Ziermann, Jürgen Teich: Interprocedural Placement-Aware Configuration Prefetching for FPGA-Based Systems. FCCM 2010: 179-182
- [c189]Daniel Ziener, Florian Baueregger, Jürgen Teich: Using the Power Side Channel of FPGAs for Communication. FCCM 2010: 237-244
- [c188]Andreas Oetken, Stefan Wildermann, Jürgen Teich, Dirk Koch: A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs. FPL 2010: 234-239
- [c187]Frank Hannig, Moritz Schmid, Jürgen Teich, Heinz Hornegger: A deeply pipelined and parallel architecture for denoising medical images. FPT 2010: 485-490
- [c186]Daniel Ziener, Florian Baueregger, Jürgen Teich: Multiplexing Methods for Power Watermarking. HOST 2010: 36-41
- [c185]Michael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich: Symbolic system level reliability analysis. ICCAD 2010: 185-189
- [c184]Andreas Kern, Christoph Schmutzler, Thilo Streichert, Michael Hübner, Jürgen Teich: Network Bandwidth Optimization of Ethernet-Based Streaming Applications in Automotive Embedded Systems. ICCCN 2010: 1-6
- [c183]Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Nils Schweer, Jürgen Teich: Virtual area management: Multitasking on dynamically partially reconfigurable devices. IPDPS Workshops 2010: 1-4
- [c182]Tobias Ziermann, Jürgen Teich: Adaptive traffic scheduling techniques for mixed real-time and streaming applications on reconfigurable hardware. IPDPS Workshops 2010: 1-4
- [c181]Rainer Kiesel, Otto Löhlein, Anestis Terzis, Martin Streubühr, Christian Haubelt, Jürgen Teich: Actor-oriented Modeling of Driver Assistance Systems for Efficient Multi-Core ECU Implementation. MBMV 2010: 117-126
- [c180]Joachim Falk, Christian Zebelein, Christian Haubelt, Jürgen Teich, Rainer Dorsch: Integrating Hardware/Firmware Verification Efforts Using SystemC High-Level Models. MBMV 2010: 137-146
- [c179]Josef Angermeier, Stefan Wildermann, Eugen Sibirko, Jürgen Teich: Placing Streaming Applications with Similarities on Dynamically Partially Reconfigurable Architectures. ReConFig 2010: 91-96
- [c178]Jens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubühr, Jürgen Teich: A system-level synthesis approach from formal application models to generic bus-based MPSoCs. ICSAMOS 2010: 118-125
- [p3]Josef Angermeier, Christophe Bobda, Mateusz Majer, Jürgen Teich: Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform. Dynamically Reconfigurable Systems 2010: 51-71
- [p2]Ali Ahmadinia, Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Dirk Koch, Mateusz Majer, Nils Schweer, Jürgen Teich, Christopher Tessars, Jan van der Veen: ReCoNodes - Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices. Dynamically Reconfigurable Systems 2010: 199-221
- [p1]Christian Haubelt, Dirk Koch, Felix Reimann, Thilo Streichert, Jürgen Teich: ReCoNets - Design Methodology for Embedded Systems Consisting of Small Networks of Reconfigurable Nodes and Connections. Dynamically Reconfigurable Systems 2010: 223-243
- [e6]Marco Platzner, Jürgen Teich, Norbert Wehn (Eds.): Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications. Springer 2010, ISBN 978-9-04-813484-7
- [e5]François Charot, Frank Hannig, Jürgen Teich, Christophe Wolinski (Eds.): 21st IEEE International Conference on Application-specific Systems Architectures and Processors, ASAP 2010, Rennes, France, 7-9 July 2010. IEEE 2010, ISBN 978-1-4244-6967-3
- [i7]Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Nils Schweer, Jürgen Teich: Maintaining Virtual Areas on FPGAs using Strip Packing with Delays. CoRR abs/1001.4493 (2010)
- [i6]Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich: No-Break Dynamic Defragmentation of Reconfigurable. CoRR abs/1012.5330 (2010)
2000 – 2009
- 2009
- [j38]Nikil Dutt, Jürgen Teich: CODES+ISSS 2007 guest editors' introduction. Design Autom. for Emb. Sys. 13(1-2): 51-52 (2009)
- [j37]Daniel Ziener, Jürgen Teich: Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs. IJAACS 2(3): 256-275 (2009)
- [j36]Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich: Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. J. Low Power Electronics 5(1): 96-105 (2009)
- [j35]Hritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, Bernard Pottier: A holistic approach for tightly coupled reconfigurable parallel processors. Microprocessors and Microsystems - Embedded Hardware Design 33(1): 53-62 (2009)
- [j34]Andreas Gerstlauer, Christian Haubelt, Andy D. Pimentel, Todor Stefanov, Daniel D. Gajski, Jürgen Teich: Electronic System-Level Synthesis Methodologies. IEEE Trans. on CAD of Integrated Circuits and Systems 28(10): 1517-1530 (2009)
- [j33]Joachim Keinert, Martin Streubühr, Thomas Schlichter, Joachim Falk, Jens Gladigau, Christian Haubelt, Jürgen Teich, Michael Meredith: SystemCoDesigner - an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications. ACM Trans. Design Autom. Electr. Syst. 14(1) (2009)
- [j32]Dirk Koch, Christian Beckhoff, Jürgen Teich: Hardware Decompression Techniques for FPGA-Based Embedded Systems. TRETS 2(2) (2009)
- [c177]Frank Hannig, Hritam Dutta, Jürgen Teich: Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning. ARCS 2009: 16-27
- [c176]Hritam Dutta, Frank Hannig, Jürgen Teich: Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis. ARCS 2009: 233-245
- [c175]Hritam Dutta, Jiali Zhai, Frank Hannig, Jürgen Teich: Impact of Loop Tiling on the Controller Logic of Acceleration Engines. ASAP 2009: 161-168
- [c174]Richard Membarth, Philipp Kutzer, Hritam Dutta, Frank Hannig, Jürgen Teich: Acceleration of Multiresolution Imaging Algorithms: A Comparative Study. ASAP 2009: 211-214
- [c173]Martin Lukasiewycz, Michael Glaß, Jürgen Teich: Exploiting data-redundancy in reliability-aware networked embedded system design. CODES+ISSS 2009: 229-238
- [c172]Martin Lukasiewycz, Michael Glaß, Jürgen Teich, Paul Milbredt: FlexRay schedule optimization of the static segment. CODES+ISSS 2009: 363-372
- [c171]Michael Glaß, Martin Lukasiewycz, Jürgen Teich, Unmesh D. Bordoloi, Samarjit Chakraborty: Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis. DAC 2009: 43-46
- [c170]Joachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, Jürgen Teich: Model-based synthesis and optimization of static multi-rate image processing algorithms. DATE 2009: 135-140
- [c169]Michael Glaß, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich: Incorporating graceful degradation into embedded system design. DATE 2009: 320-323
- [c168]Martin Lukasiewycz, Martin Streubühr, Michael Glaß, Christian Haubelt, Jürgen Teich: Combined system synthesis and communication architecture exploration for MPSoCs. DATE 2009: 472-477
- [c167]Tobias Ziermann, Stefan Wildermann, Jürgen Teich: CAN+: A new backward-compatible Controller Area Network (CAN) protocol with up to 16× higher data rates. DATE 2009: 1088-1093
- [c166]Dirk Koch, Christian Beckhoff, Jürgen Teich: Minimizing Internal Fragmentation by Fine-Grained Two-Dimensional Module Placement for Runtime Reconfiguralble Systems. FCCM 2009: 251-254
- [c165]Joon Edward Sim, Weng-Fai Wong, Jürgen Teich: Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators. FCCM 2009: 279-282
- [c164]Martin Streubühr, Jens Gladigau, Christian Haubelt, Jürgen Teich: Efficient approximately-timed performance modeling for architectural exploration of MPSoCs. FDL 2009: 1-6
- [c163]Dirk Koch, Christian Beckhoff, Jürgen Teich: A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs. FPGA 2009: 253-256
- [c162]Stefan Wildermann, Gregor Walla, Tobias Ziermann, Jürgen Teich: Self-organizing multi-cue fusion for FPGA-based embedded imaging. FPL 2009: 132-137
- [c161]Josef Angermeier, Abdulazim Amouri, Jürgen Teich: General methodology for mapping iterative approximation algorithms to adaptive dynamically partially reconfigurable systems. FPL 2009: 302-307
- [c160]Jürgen Teich: From dynamic reconfiguration to self-reconfiguration: Invasive algorithms and architectures. FPT 2009: 11-12
- [c159]Abdulazim Amouri, Farhadur Arifin, Frank Hannig, Jürgen Teich: FPGA implementation of an invasive computing architecture. FPT 2009: 135-142
- [c158]Vahid Lari, Frank Hannig, Jürgen Teich: System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance. ICPP Workshops 2009: 528-534
- [c157]Jens Gladigau, Christian Haubelt, Martin Streubühr, Jürgen Teich, Axel Schneider, Joachim Knäblein, Michael Lindig: Testfallgenerierung für SystemC-Designs mit abstrakten Modellbeschreibungen. MBMV 2009: 157-166
- [c156]Richard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich: Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors. SAMOS 2009: 277-288
- [c155]Stefan Wildermann, Tobias Ziermann, Jürgen Teich: Self-organizing Bandwidth Sharing in Priority-Based Medium Access. SASO 2009: 144-153
- 2008
- [j31]Jürgen Teich: Invasive Algorithms and Architectures (Invasive Algorithmen und Architekturen). it - Information Technology 50(5): 300-310 (2008)
- [j30]Sándor P. Fekete, Jan van der Veen, Ali Ahmadinia, Diana Göhringer, Mateusz Majer, Jürgen Teich: Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device. IEEE Trans. VLSI Syst. 16(9): 1210-1219 (2008)
- [j29]Daniel Ziener, Jürgen Teich: Power Signature Watermarking of IP Cores for FPGAs. Signal Processing Systems 51(1): 123-136 (2008)
- [c154]Josef Angermeier, Ulrich Batzer, Mateusz Majer, Jürgen Teich, Christopher Claus, Walter Stechele: Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System. ARC 2008: 148-158
- [c153]Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Jürgen Teich: PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. ARC 2008: 284-289
- [c152]Thilo Streichert, Michael Glaß, Rolf Wanka, Christian Haubelt, Jürgen Teich: Topology-Aware Replica Placement in Fault-Tolerant Embedded Networks. ARCS 2008: 23-37
- [c151]Robert Brendle, Thilo Streichert, Dirk Koch, Christian Haubelt, Jürgen Teich: Dynamic Reconfiguration of FlexRay Schedules for Response Time Reduction in Asynchronous Fault-Tolerant Networks. ARCS 2008: 117-129
- [c150]Joachim Keinert, Christian Haubelt, Jürgen Teich: Synthesis of Multi-dimensional High-Speed FIFOs for Out-of-Order Communication. ARCS 2008: 130-143
- [c149]Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich: Efficient symbolic multi-objective design space exploration. ASP-DAC 2008: 691-696
- [c148]Daniel Ziener, Jürgen Teich: Concepts for Autonomous Control Flow Checking for Embedded CPUs. ATC 2008: 234-248
- [c147]Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich: A feasibility-preserving local search operator for constrained discrete optimization problems. IEEE Congress on Evolutionary Computation 2008: 1968-1975
- [c146]Felix Reimann, Michael Glabeta, Martin Lukasiewycz, Joachim Keinert, Christian Haubelt, Jürgen Teich: Symbolic voter placement for dependability-aware system synthesis. CODES+ISSS 2008: 237-242
- [c145]Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich, Richard Regler, Bardo Lang: Concurrent topology and routing optimization in automotive network integration. DAC 2008: 626-629
- [c144]Michael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich: Symbolic Reliability Analysis and Optimization of ECU Networks. DATE 2008: 158-163
- [c143]Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig: Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. DSD 2008: 345-352
- [c142]Rainer Schaffer, Renate Merker, Frank Hannig, Jürgen Teich: Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. DSD 2008: 391-398
- [c141]Joachim Falk, Joachim Keinert, Christian Haubelt, Jürgen Teich, Shuvra S. Bhattacharyya: A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications. EMSOFT 2008: 189-198
- [c140]Dirk Koch, Christian Haubelt, Jürgen Teich: Efficient Reconfigurable On-Chip Buses for FPGAs. FCCM 2008: 287-290
- [c139]Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig: Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. FCCM 2008: 306-309
- [c138]Jens Gladigau, Christian Haubelt, Jürgen Teich: Symbolic Quasi-Static Scheduling of Actor-Oriented SystemC Models. FDL 2008: 1-6
- [c137]Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich: No-break dynamic defragmentation of reconfigurable devices. FPL 2008: 113-118
- [c136]Dirk Koch, Christian Beckhoff, Jürgen Teich: ReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS. FPL 2008: 119-124
- [c135]Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker: Fine grain reconfigurable architectures. FPL 2008: 348
- [c134]Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner: Coarse-grained reconfiguration. FPL 2008: 349
- [c133]Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig: Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures. FPL 2008: 391-396
- [c132]Christopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jürgen Teich: A comparison of embedded reconfigurable video-processing architectures. FPL 2008: 587-590
- [c131]Moritz Schmid, Daniel Ziener, Jürgen Teich: Netlist-level IP protection by watermarking for LUT-based FPGAs. FPT 2008: 209-216
- [c130]Stefan Wildermann, Jürgen Teich: A Sequential Learning Resource Allocation Network for Image Processing Applications. HIS 2008: 132-137
- [c129]Josef Angermeier, Jürgen Teich: Heuristics for scheduling reconfigurable devices with consideration of reconfiguration overheads. IPDPS 2008: 1-8
- [c128]Jens Gladigau, Frank Blendinger, Christian Haubelt, Jürgen Teich: Symbolische Modellprüfung Aktor-orientierter High-level SystemC-Modelle mit Intervalldiagrammen. MBMV 2008: 109-118
- [c127]Frank Hannig, Holger Ruckdeschel, Jürgen Teich: The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications. MBMV 2008: 129-138
- [c126]Martin Streubühr, Michael Jäntsch, Christian Haubelt, Jürgen Teich, Axel Schneider: Semi-Automatic Generation of mixed Hardware/Software Prototypes from Simulink Models. MBMV 2008: 139-148
- [c125]Christian Zebelein, Joachim Falk, Christian Haubelt, Jürgen Teich: Classification of General Data Flow Actors into Known Models of Computation. MEMOCODE 2008: 119-128
- [c124]Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich: Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. PATMOS 2008: 307-317
- [c123]Martin Lukasiewycz, Michael Glaß, Jürgen Teich: A Feasibility-Preserving Crossover and Mutation Operator for Constrained Combinatorial Problems. PPSN 2008: 919-928
- [c122]Stefan Wildermann, Jürgen Teich: 3D Person Tracking with a Color-Based Particle Filter. RobVis 2008: 327-340
- [c121]Mateusz Majer, Stefan Wildermann, Josef Angermeier, Stefan Hanke, Jürgen Teich: Co-design Architecture and Implementation for Point-Based Rendering on FPGAs. IEEE International Workshop on Rapid System Prototyping 2008: 142-148
- [c120]Michael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich: Symbolic Reliability Analysis of Self-healing Networked Embedded Systems. SAFECOMP 2008: 139-152
- [c119]Michael Glaß, Martin Lukasiewycz, Rolf Wanka, Christian Haubelt, Jürgen Teich: Multi-objective routing and topology optimization in networked embedded systems. ICSAMOS 2008: 74-81
- 2007
- [b2]Jürgen Teich, Christian Haubelt: Digitale Hardware/Software-Systeme: Synthese und Optimierung, 2. Auflage. eXamen.press, Springer 2007, ISBN 978-3-540-46822-6
- [j28]Neil Bergmann, Marco Platzner, Jürgen Teich: Dynamically Reconfigurable Architectures. EURASIP J. Emb. Sys. 2007 (2007)
- [j27]Christian Haubelt, Joachim Falk, Joachim Keinert, Thomas Schlichter, Martin Streubühr, Andreas Deyhle, Andreas Hadert, Jürgen Teich: A SystemC-Based Design Methodology for Digital Signal Processing Systems. EURASIP J. Emb. Sys. 2007 (2007)
- [j26]Jürgen Teich: Reconfigurable Computing Systems (Rekonfigurierbare Rechensysteme). it - Information Technology 49(3): 139- (2007)
- [j25]Josef Angermeier, Diana Göhringer, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen: The Erlangen Slot Machine - A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens). it - Information Technology 49(3): 143- (2007)
- [j24]Hritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich: Efficient control generation for mapping nested loop programs onto processor arrays. Journal of Systems Architecture 53(5-6): 300-309 (2007)
- [j23]Thilo Streichert, Michael Glaß, Christian Haubelt, Jürgen Teich: Design space exploration of reliable networked embedded systems. Journal of Systems Architecture 53(10): 751-763 (2007)
- [j22]Mateusz Majer, Jürgen Teich, Ali Ahmadinia, Christophe Bobda: The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer. VLSI Signal Processing 47(1): 15-31 (2007)
- [c118]Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement: Modeling of Interconnection Networks in Massively Parallel Processor Architectures. ARCS 2007: 268-282
- [c117]Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich: SAT-decoding in evolutionary algorithms for discrete constrained optimization problems. IEEE Congress on Evolutionary Computation 2007: 935-942
- [c116]Michael Glaß, Martin Lukasiewycz, Thilo Streichert, Christian Haubelt, Jürgen Teich: Interactive presentation: Reliability-aware system synthesis. DATE 2007: 409-414
- [c115]Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet: A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. ERSA 2007: 14-24
- [c114]Joachim Keinert, Joachim Falk, Christian Haubelt, Jürgen Teich: Actor-Oriented Modeling and Simulation of Sliding Window Image Processing Algorithms. ESTImedia 2007: 113-118
- [c113]Jens Gladigau, Christian Haubelt, Bernhard Niemann, Jürgen Teich: Mapping Actor-Oriented Models to TLM Architectures. FDL 2007: 128-133
- [c112]Dirk Koch, Christian Haubelt, Jürgen Teich: Efficient hardware checkpointing: concepts, overhead analysis, and implementation. FPGA 2007: 188-196
- [c111]Dirk Koch, Christian Beckhoff, Jürgen Teich: Bitstream Decompression for High Speed FPGA Configuration from Slow Memories. FPT 2007: 161-168
- [c110]Dirk Koch, Christian Haubelt, Thilo Streichert, Jürgen Teich: Modeling and Synthesis of Hardware-Software Morphing. ISCAS 2007: 2746-2749
- [c109]Martin Streubühr, Carsten Riedel, Christian Haubelt, Jürgen Teich: System Level Modeling and Performance Simulation for Dynamic Reconfigurable Computing Systems in SystemC. MBMV 2007: 59-68
- [c108]Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier: Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC 2007: 61-68
- [c107]Joachim Keinert, Christian Haubelt, Jürgen Teich: Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data Flow. ICSAMOS 2007: 161-168
- [c106]Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich: Solving Multi-objective Pseudo-Boolean Problems. SAT 2007: 56-69
- [c105]Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich: Efficient event-driven simulation of parallel processor architectures. SCOPES 2007: 71-80
- [e4]Soonhoi Ha, Kiyoung Choi, Nikil D. Dutt, Jürgen Teich (Eds.): Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007. ACM 2007, ISBN 978-1-59593-824-4
- [e3]Christian Haubelt, Jürgen Teich (Eds.): Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Erlangen, Germany, March 5-7, 2007. Shaker 2007
- 2006
- [j21]Thilo Streichert, Dirk Koch, Christian Haubelt, Jürgen Teich: Modeling and Design of Fault-Tolerant and Self-Adaptive Reconfigurable Networked Embedded Systems. EURASIP J. Emb. Sys. 2006 (2006)
- [j20]Frank Hannig, Hritam Dutta, Jürgen Teich: Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology. IJES 2(1/2): 114-127 (2006)
- [j19]Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich: Higher-Dimensional Packing with Order Constraints. SIAM J. Discrete Math. 20(4): 1056-1078 (2006)
- [j18]Jürgen Teich, Shuvra S. Bhattacharyya: Analysis of Dataflow Programs with Interval-limited Data-rates. VLSI Signal Processing 43(2-3): 247-258 (2006)
- [c104]Hritam Dutta, Frank Hannig, Jürgen Teich: Controller Synthesis for Mapping Partitioned Programs on Array Architectures. ARCS 2006: 176-190
- [c103]Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Jürgen Teich: A Flexible Reconfiguration Manager for the Erlangen Slot Machine. ARCS Workshops 2006: 183-194
- [c102]Dirk Koch, Thilo Streichert, Steffen Dittrich, Christian Strengert, Christian Haubelt, Jürgen Teich: An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks. ARCS 2006: 202-216
- [c101]Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger: A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. ASAP 2006: 331-340
- [c100]Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich: A Generic Framework for Rapid Prototyping of System-on-Chip Designs. CDES 2006: 189-195
- [c99]Jürgen Teich: Are current ESL tools meeting the requirements of advanced embedded systems? CODES+ISSS 2006: 166
- [c98]Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas: 06141 Executive Summary -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2006
- [c97]Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas: 06141 Abstracts Collection -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2006
- [c96]Diana Göhringer, Mateusz Majer, Jürgen Teich: Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine. Dynamically Reconfigurable Architectures 2006
- [c95]Martin Streubühr, Joachim Falk, Christian Haubelt, Jürgen Teich, Rainer Dorsch, Thomas Schlipf: Task-accurate performance modeling in SystemC for real-time multi-processor architectures. DATE 2006: 480-481
- [c94]Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich: Symbolic Archive Representation for a Fast Nondominance Test. EMO 2006: 111-125
- [c93]Dirk Koch, Matthiaas Koerber, Jürgen Teich: Searching RC5-Keys with Distributed Reconfigurable Computing. ERSA 2006: 42-48
- [c92]Jürgen Teich, Stefanos Kaxiras, Toomas P. Plaks, Krisztián Flautner: Topic 18: Embedded Parallel Systems. Euro-Par 2006: 1179
- [c91]Joachim Falk, Christian Haubelt, Jürgen Teich: Efficient Representation and Simulation of Model-Based Designs. FDL 2006: 129-135
- [c90]Sándor P. Fekete, Jan van der Veen, Mateusz Majer, Jürgen Teich: Minimizing Communication Cost for Reconfigurable Slot Modules. FPL 2006: 1-6
- [c89]Daniel Ziener, Stefan Assmus, Jürgen Teich: Identifying FPGA IP-Cores Based on Lookup Table Content Analysis. FPL 2006: 1-6
- [c88]Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich: A highly parameterizable parallel processor array architecture. FPT 2006: 105-112
- [c87]Daniel Ziener, Jürgen Teich: FPGA core watermarking based on power signature analysis. FPT 2006: 205-212
- [c86]Thomas Schlichter, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich: Improving System Level Design Space Exploration by Incorporating SAT-Solvers into Multi-Objective Evolutionary Algorithms. ISVLSI 2006: 309-316
- [c85]Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Renate Merker: An Architecture Description Language for Massively Parallel Processor Architectures. MBMV 2006: 11-20
- [c84]Hritam Dutta, Frank Hannig, Jürgen Teich: Hierarchical Partitioning for Piecewise Linear Algorithms. PARELEC 2006: 153-160
- [c83]Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich: A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. ReCoSoC 2006: 31-37
- [c82]Thilo Streichert, Christian Haubelt, Jürgen Teich: Multi-Objective Topology Optimization for Networked Embedded Systems. ICSAMOS 2006: 93-98
- [c81]Thilo Streichert, Christian Strengert, Christian Haubelt, Jürgen Teich: Dynamic task binding for hardware/software reconfigurable networks. SBCCI 2006: 38-43
- [e2]Peter M. Athanas, Jürgen Becker, Gordon J. Brebner, Jürgen Teich (Eds.): Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006. Dagstuhl Seminar Proceedings 06141, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany 2006
- 2005
- [j17]Ali Ahmadinia, Christophe Bobda, Jürgen Teich: Online placement for dynamically reconfigurable devices. IJES 1(3/4): 165-178 (2005)
- [c80]Thomas Schlichter, Christian Haubelt, Frank Hannig, Jürgen Teich: Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems. ASAP 2005: 9-14
- [c79]Christian Haubelt, Stephan Otto, Cornelia Grabbe, Jürgen Teich: A system-level approach to hardware reconfigurable systems. ASP-DAC 2005: 298-301
- [c78]Thilo Streichert, Christian Haubelt, Jürgen Teich: Online hardware/software partitioning in networked embedded systems. ASP-DAC 2005: 982-985
- [c77]S. Helwig, Christian Haubelt, Jürgen Teich: Modeling and analysis of indirect communication in particle swarm optimization. Congress on Evolutionary Computation 2005: 1246-1253
- [c76]Sanaz Mostaghim, Jürgen Teich: A New Approach on Many Objective Diversity Measurement. Practical Approaches to Multi-Objective Optimization 2005
- [c75]Thilo Streichert, Christian Haubelt, Jürgen Teich: Distributed HW/SW-Partitioning for Embedded Reconfigurable Networks. DATE 2005: 894-895
- [c74]Christian Haubelt, Jürgen Gamenik, Jürgen Teich: Initial Population Construction for Convergence Improvement of MOEAs. EMO 2005: 191-205
- [c73]Frank Hannig, Jürgen Teich: Output Serialization for FPGA-based and Coarse-grained Processor Arrays. ERSA 2005: 78-84
- [c72]Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich: Defragmenting the Module Layout of a Partially Reconfigurable Device. ERSA 2005: 92-104
- [c71]Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich, Sándor P. Fekete, Jan van der Veen: The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform. FCCM 2005: 319-320
- [c70]Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen: DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices. FPL 2005: 153-158
- [c69]Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich: The Erlangen Slot Machine: Increasing Flexibility in FPGA-Based Reconfigurable Platforms. FPT 2005: 37-42
- [c68]Thomas Schlichter, Christian Haubelt, Jürgen Teich: Improving EA-based design space exploration by utilizing symbolic feasibility tests. GECCO 2005: 1945-1952
- [c67]Christian Haubelt, Marek Jersak, Kai Richter, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich, Lothar Thiele: SPI-Workbench - Modellierung, Analyse und Optimierung eingebetteter Systeme. GI Jahrestagung (2) 2005: 693-697
- [c66]Mateusz Majer, Christophe Bobda, Ali Ahmadinia, Jürgen Teich: Packet Routing in Dynamically Changing Networks on Chip. IPDPS 2005
- [c65]Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys: Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC 2005: 27-34
- [c64]Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen: A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices. IEEE International Workshop on Rapid System Prototyping 2005: 84-90
- [c63]Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich: Automatic FIR Filter Generation for FPGAs. SAMOS 2005: 51-61
- [i5]Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen: A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices. CoRR abs/cs/0503066 (2005)
- [i4]Jan van der Veen, Sándor P. Fekete, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich: Defragmenting the Module Layout of a Partially Reconfigurable Device. CoRR abs/cs/0505005 (2005)
- [i3]Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen: DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices. CoRR abs/cs/0510039 (2005)
- 2004
- [j16]Neal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler: Systematic integration of parameterized local search into evolutionary algorithms. IEEE Trans. Evolutionary Computation 8(2): 137-155 (2004)
- [c62]Ali Ahmadinia, Christophe Bobda, Jürgen Teich: A Dynamic Scheduling and Placement Algorithm for Reconfigurable Hardware. ARCS 2004: 125-139
- [c61]Christophe Bobda, Ali Ahmadinia, Jürgen Teich: Generation of Distributed Arithmetic Designs for Reconfigurable Application. ARCS Workshops 2004: 205-214
- [c60]Frank Hannig, Jürgen Teich: Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals. ASAP 2004: 17-27
- [c59]Dirk Koch, Jürgen Teich: Platform-independent methodology for partial reconfiguration. Conf. Computing Frontiers 2004: 398-403
- [c58]Ali Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan van der Veen: Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices. FPL 2004: 847-851
- [c57]Christophe Bobda, Mateusz Majer, Dirk Koch, Ali Ahmadinia, Jürgen Teich: A Dynamic NoC Approach for Communication in Reconfigurable Devices. FPL 2004: 1032-1036
- [c56]Neal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler: Systematic Integration of Parameterized Local Search Techniques in Evolutionary Algorithms. GECCO (2) 2004: 383-384
- [c55]Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich: A New Approach for On-line Placement on Reconfigurable Devices. IPDPS 2004
- [c54]Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich: Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration. IPDPS 2004
- [c53]Frank Hannig, Hritam Dutta, Jürgen Teich: Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology. IPDPS 2004
- [c52]
- [c51]Christian Haubelt, Dirk Koch, Jürgen Teich: Basic OS Support for Distributed Reconfigurable Hardware. SAMOS 2004: 30-38
- [c50]Jürgen Teich, Shuvra S. Bhattacharyya: Analysis of Dataflow Programs with Interval-Limited Data-Rates. SAMOS 2004: 507-518
- [c49]Alexey Kupriyanov, Frank Hannig, Jürgen Teich: High-Speed Event-Driven RTL Compiled Simulation. SAMOS 2004: 519-529
- [c48]Ali Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich: Task scheduling for heterogeneous reconfigurable computers. SBCCI 2004: 22-27
- [i2]Ali Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan van der Veen: Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices. CoRR cs.DS/0406035 (2004)
- 2003
- [j15]Marcus Bednara, Klaus Danne, Markus Deppe, Oliver Oberschelp, Frank Slomka, Jürgen Teich: Design and Implementation of Digital Linear Control Systems on Reconfigurable Hardware. EURASIP J. Adv. Sig. Proc. 2003(6): 594-602 (2003)
- [j14]Dirk Fischer, Jürgen Teich, Ralph Weper, Michael Thies: BUILDABONG: A Framework for Architecture/Compiler Co-Exploration for ASIPs. Journal of Circuits, Systems, and Computers 12(3): 353- (2003)
- [j13]Marcus Bednara, Jürgen Teich: Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms. The Journal of Supercomputing 26(2): 149-165 (2003)
- [c47]Christian Haubelt, Jürgen Teich: Accelerating design space exploration using pareto-front arithmetics. ASP-DAC 2003: 525-531
- [c46]Jens Gerling, Oliver Stübbe, Jürgen Schrage, Gerd Mrozynski, Jürgen Teich: Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects. DATE 2003: 11110-11111
- [c45]Christian Haubelt, Jürgen Teich, Rainer Feldmann, Burkhard Monien: SAT-Based Techniques in System Synthesis. DATE 2003: 11168-11169
- [c44]Oliver Schütze, Sanaz Mostaghim, Michael Dellnitz, Jürgen Teich: Covering Pareto Sets by Multilevel Evolutionary Subdivision Techniques. EMO 2003: 118-132
- [c43]Christian Haubelt, Sanaz Mostaghim, Jürgen Teich, Ambrish Tyagi: Solving Hierarchical Optimization Problems Using MOEAs. EMO 2003: 162-176
- [c42]Rainer Feldmann, Christian Haubelt, Burkhard Monien, Jürgen Teich: Fault Tolerances Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques. FPL 2003: 478-487
- [c41]Ali Ahmadinia, Christophe Bobda, Jürgen Teich: Temporal task clustering for online placement on reconfigurable hardware. FPT 2003: 359-362
- [c40]Christophe Bobda, Klaus Danne, Ali Ahmadinia, Jürgen Teich: A new approach for reconfigurable massively parallel computers. FPT 2003: 391-394
- [c39]Cornelia Grabbe, Marcus Bednara, Joachim von zur Gathen, Jamshid Shokrollahi, Jürgen Teich: A High Performance VLIW Processor for Finite Field Arithmetic. IPDPS 2003: 189
- [c38]Cornelia Grabbe, Marcus Bednara, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi: FPGA designs of parallel high performance GF(2233) multipliers. ISCAS (2) 2003: 268-271
- [c37]Christian Haubelt, Dirk Koch, Jürgen Teich: ReCoNet: Modeling and Implementation of Fault Tolerant Distributed Reconfigurable Hardware. SBCCI 2003: 343-348
- [c36]Ali Ahmadinia, Jürgen Teich: Speeding up Online Placement for XILINX FPGAs by Reducing Configuration Overhead. VLSI-SOC 2003: 118-122
- [i1]Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich: Higher-Dimensional Packing with Order Constraints. CoRR cs.DS/0308006 (2003)
- 2002
- [j12]Dirk Ziegenbein, Kai Richter, Rolf Ernst, Lothar Thiele, Jürgen Teich: SPI - a system model for heterogeneously specified embedded systems. IEEE Trans. VLSI Syst. 10(4): 379-389 (2002)
- [c35]Dirk Fischer, Jürgen Teich, Michael Thies, Ralph Weper: Efficient architecture/compiler co-exploration for ASIPs. CASES 2002: 27-34
- [c34]Jürgen Teich, Markus Köster: (Self-)reconfigurable Finite State Machines: Theory and Implementation. DATE 2002: 559-566
- [c33]Christian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst: System Design for Flexibility. DATE 2002: 854-861
- [c32]Marcus Bednara, M. Daldrup, Joachim von zur Gathen, Jamshid Shokrollahi, Jürgen Teich: Reconfigurable Implementation of Elliptic Curve Crypto Algorithms. IPDPS 2002
- [c31]Marcus Bednara, M. Daldrup, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi: Tradeoff analysis of FPGA based elliptic curve cryptography. ISCAS (5) 2002: 797-800
- [c30]Christian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst: Modellierung rekonfigurierbarer Systemarchitekturen. MBMV 2002: 163-171
- [c29]Christian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst: Flexibility/Cost-Tradeoffs of Platform-Based Systems. Embedded Processor Design Challenges 2002: 38-56
- [c28]Jürgen Teich, Lothar Thiele: Exact Partitioning of Affine Dependence Algorithms. Embedded Processor Design Challenges 2002: 135-153
- [c27]Marcus Bednara, Frank Hannig, Jürgen Teich: Generation of Distributed Loop Control. Embedded Processor Design Challenges 2002: 154-170
- [c26]
- [e1]Ed F. Deprettere, Jürgen Teich, Stamatis Vassiliadis (Eds.): Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS. Lecture Notes in Computer Science 2268, Springer 2002, ISBN 3-540-43322-8
- 2001
- [j11]Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich: Extending Partial Suborders. Electronic Notes in Discrete Mathematics 8: 34-37 (2001)
- [j10]Jürgen Teich, Sándor P. Fekete, Jörg Schepers: Optimization of Dynamic Hardware Reconfigurations. The Journal of Supercomputing 19(1): 57-75 (2001)
- [j9]Karsten Strehl, Lothar Thiele, Matthias Gries, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich: FunState-an internal design representation for codesign. IEEE Trans. VLSI Syst. 9(4): 524-544 (2001)
- [c25]Dirk Fischer, Jürgen Teich, Ralph Weper, Uwe Kastens, Michael Thies: Design space characterization for architecture/compiler co-exploration. CASES 2001: 108-115
- [c24]Neal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler: Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors. CODES 2001: 243-248
- [c23]Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich: Optimal FPGA module placement with temporal precedence constraints. DATE 2001: 658-667
- [c22]
- [c21]Frank Hannig, Jürgen Teich: Design Space Exploration for Massively Parallel Processor Arrays. PaCT 2001: 51-65
- [c20]Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich: Higher-Dimensional Packing with Order Constraints. WADS 2001: 300-312
- 2000
- [j8]Lothar Thiele, Jürgen Teich, Karsten Strehl: Regular state machines. Parallel Algorithms Appl. 15(3-4): 265-300 (2000)
- [j7]Eckart Zitzler, Jürgen Teich, Shuvra S. Bhattacharyya: Evolutionary algorithms for the synthesis of embedded software. IEEE Trans. VLSI Syst. 8(4): 452-455 (2000)
- [j6]Eckart Zitzler, Jürgen Teich, Shuvra S. Bhattacharyya: Multidimensional Exploration of Software Implementations for DSP Algorithms. VLSI Signal Processing 24(1): 83-98 (2000)
- [c19]Marcus Bednara, Oliver Beyer, Jürgen Teich, Rolf Wanka: Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter. ASAP 2000: 299-308
- [c18]Jürgen Teich, Philipp W. Kutter, Ralph Weper: Description and Simulation of Microprocessor Instruction Sets Using ASMs. Abstract State Machines 2000: 266-286
- [c17]Jürgen Teich, Ralph Weper, Dirk Fischer, Stefan Trinkert: A joined architecture/compiler design environment for ASIPs. CASES 2000: 26-33
- [c16]F. Cieslok, H. Esau, Jürgen Teich: EXPLORA - Generic Design Space Exploration during Embedded System Synthesis. DIPES 2000: 215-226
1990 – 1999
- 1999
- [c15]Jürgen Teich, Eckart Zitzler, Shuvra S. Bhattacharyya: 3D exploration of software schedules for DSP algorithms. CODES 1999: 168-172
- [c14]Karsten Strehl, Lothar Thiele, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich: Scheduling hardware/software systems using symbolic techniques. CODES 1999: 173-177
- [c13]Kai Richter, Dirk Ziegenbein, Rolf Ernst, Lothar Thiele, Jürgen Teich: Representation of Function Variants for Embedded System Optimization and Synthesis. DAC 1999: 517-522
- [c12]Lothar Thiele, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich: FunState - an internal design representation for codesign. ICCAD 1999: 558-565
- [c11]Dirk Ziegenbein, Kai Richter, Rolf Ernst, Lothar Thiele, Jürgen Teich: SPI -- An Internal Representation for Heterogeneously Specified Embedded Systems. MBMV 1999: 160-169
- [c10]Jürgen Teich, Sándor P. Fekete, Jörg Schepers: Compile-time Optimization of Dynamic Hardware Reconfigurations. PDPTA 1999: 1097-1103
- 1998
- [j5]Tobias Blickle, Jürgen Teich, Lothar Thiele: System-Level Synthesis Using Evolutionary Algorithms. Design Autom. for Emb. Sys. 3(1): 23-58 (1998)
- [c9]Dirk Ziegenbein, Rolf Ernst, Kai Richter, Jürgen Teich, Lothar Thiele: Combining multiple models of computation for scheduling and allocation. CODES 1998: 9-13
- [c8]Michael Eisenring, Jürgen Teich: Domain-specific interface generation from dataflow specifications. CODES 1998: 43-47
- [c7]
- [c6]Dirk Ziegenbein, Kai Richter, Rolf Ernst, Jürgen Teich, Lothar Thiele: Representation of process mode correlation for scheduling. ICCAD 1998: 54-61
- [c5]Jürgen Teich, Eckart Zitzler, Shuvra S. Bhattacharyya: Buffer Memory Optimization in DSP Applications - An Evolutionary Approach. PPSN 1998: 885-896
- 1997
- [b1]Jürgen Teich: Digitale Hardware/Software-Systeme - Synthese und Optimierung. Springer 1997, ISBN 978-3-540-62433-2, pp. I-XVII, 1-514
- [j4]Jürgen Teich, Lothar Thiele, Sundararajan Sriram, Michael Martin: Performance analysis and optimization of mixed asynchronous synchronous systems. IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 473-484 (1997)
- [j3]Jürgen Teich, Lothar Thiele, Lee Z. Zhang: Partitioning Processor Arrays under Resource Constraints. VLSI Signal Processing 17(1): 5-20 (1997)
- [c4]Jürgen Teich, Tobias Blickle, Lothar Thiele: An evolutionary approach to system-level synthesis. CODES 1997: 167-172
- 1996
- [c3]Jürgen Teich, Lothar Thiele, Li Zhang: Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources. ASAP 1996: 131-144
- 1995
- [c2]Christian Schwarz, Jürgen Teich, Alek Vainshtein, Emo Welzl, Brian L. Evans: Minimal Enclosing Parallelogram with Application. Symposium on Computational Geometry 1995: C34-C35
- [c1]Jürgen Teich, Lothar Thiele, Edward A. Lee: Modeling and simulation of heterogeneous real-time systems based on a deterministic discrete event model. ISSS 1995: 156-161
- 1993
- [j2]Jürgen Teich, Lothar Thiele: Partitioning of processor arrays: a piecewise regular approach. Integration 14(3): 297-332 (1993)
- 1991
- [j1]