Hidehiro Takata

Takuya Sawada, Taku Toshikawa, Kumpei Yoshikawa, Hidehiro Takata, Koji Nii, Makoto Nagata: Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation. IEICE Transactions 95-C(4): 586-593 (2012)

Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada: On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction. IEICE Transactions 95-C(4): 643-650 (2012)

Ryo Takahashi, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai: Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature. IEEE Trans. on Circuits and Systems 59-II(12): 918-921 (2012)

Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada: On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch. IEICE Transactions 94-C(4): 511-519 (2011)

Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada: Decoupling capacitance boosting for on-chip resonant supply noise reduction. DDECS 2011: 111-114

Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada: On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure. ESSCIRC 2011: 183-186

Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara: Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scaling. ACM Trans. Design Autom. Electr. Syst. 15(2) (2010)

Yu Pu, Xin Zhang, Jim Huang, Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano, Makoto Takamiya, Takayasu Sakurai: Misleading energy and performance claims in sub/near threshold digital systems. ICCAD 2010: 625-631

Mitsuya Fukazawa, Masanori Kurimoto, Rei Akiyama, Hidehiro Takata, Makoto Nagata: Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations. IEICE Transactions 92-C(4): 475-482 (2009)

Masanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara: Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling. DAC 2008: 884-889

Hiroaki Suzuki, Masanori Kurimoto, Tadao Yamanaka, Hidehiro Takata, Hiroshi Makino, Hirofumi Shinohara: Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology. ISLPED 2008: 15-20

Kazutami Arimoto, Toshihiro Hattori, Hidehiro Takata, Atsushi Hasegawa, Toru Shimizu: Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS. IEICE Transactions 90-C(4): 657-665 (2007)

Niichi Itoh, Yasumasa Tsukamoto, Takeshi Shibagaki, Koji Nii, Hidehiro Takata, Hiroshi Makino: A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. ISCAS (1) 2005: 73-76

Toshiyuki Tamura, Shinji Komori, Fumiyasu Asai, Hirono Tsubota, Hisakazu Sato, Hidehiro Takata, Yoshihiro Seguchi, Takeshi Tokuda, Hiroaki Terada: A Data-Driven Architecture for Distributed Parallel Processing. ICCD 1991: 218-224