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2010 – today
- 2017
[c25]Itsuo Takanami, Masaru Fukushi:
A Built-in Circuit for Self-Repairing Mesh-Connected Processor Arrays with Spares on Diagonal. PRDC 2017: 110-117- 2016
- [j68]Itsuo Takanami, Tadayoshi Horita, Masakazu Akiba, Mina Terauchi, Tsuneo Kanno:
A Built-in Self-repair Circuit for Restructuring Mesh-Connected Processor Arrays by Direct Spare Replacement. Trans. Computational Science 27: 97-119 (2016) - 2015
- [j67]Tadayoshi Horita, Itsuo Takanami, Masakazu Akiba, Mina Terauchi, Tsuneo Kanno:
An FPGA-Based Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Perceptron (Full Version). Trans. Computational Science 25: 148-171 (2015) - 2014
- [j66]Tadayoshi Horita, Itsuo Takanami, Kazuhiro Nishimura:
Multilayer Perceptrons Which Are Tolerant to Multiple Faults and Learnings to Realize Them. Trans. Computational Science 22: 42-63 (2014) - [c24]Tadayoshi Horita, Itsuo Takanami, Masakazu Akiba, Mina Terauchi, Tsuneo Kanno:
A GPGPU-Based Acceleration of Fault-Tolerant MLP Learnings. MCSoC 2014: 245-252 - 2013
- [j65]Tadayoshi Horita, Itsuo Takanami:
An FPGA-based multiple-weight-and-neuron-fault tolerant digital multilayer perceptron. Neurocomputing 99: 570-574 (2013) - 2012
- [c23]Itsuo Takanami, Tadayoshi Horita:
A Built-in Circuit for Self-Repairing Mesh-Connected Processor Arrays by Direct Spare Replacement. PRDC 2012: 96-104 - 2011
- [j64]Tadayoshi Horita, Itsuo Takanami:
An FPGA-Based Fault-Tolerant 2D Systolic Array for Matrix Multiplications. Trans. Computational Science 13: 108-124 (2011) - 2010
- [j63]Tadayoshi Horita, Itsuo Takanami:
An FPGA-based fast classifier with high generalization property. SIGARCH Computer Architecture News 38(4): 21-26 (2010)
2000 – 2009
- 2009
- [c22]Tadayoshi Horita, Itsuo Takanami:
An Implementation of a Fault-Tolerant 2D Systolic Array on FPGAs and Its Evaluation. PDPTA 2009: 136-142 - [c21]Kazuhiro Nishimura, Tadayoshi Horita, Masato Otsu, Itsuo Takanami:
Novel Value Injection Learning Methods Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant. PDPTA 2009: 546-552 - 2008
- [j62]Tadayoshi Horita, Yuuji Katou, Itsuo Takanami:
An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches. IEICE Transactions 91-A(2): 623-632 (2008) - [j61]Tadayoshi Horita, Itsuo Takanami, Masatoshi Mori:
Learning Algorithms Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant. IEICE Transactions 91-D(4): 1168-1175 (2008) - 2006
- [c20]Tadayoshi Horita, Takurou Murata, Itsuo Takanami:
A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network. DFT 2006: 554-562 - 2004
- [j60]Itsuo Takanami:
Self-Reconfiguring of 1½-Track-Switch Mesh Arrays with Spares on One Row and One Column by Simple Built-in Circuit. IEICE Transactions 87-D(10): 2318-2328 (2004) - 2002
- [c19]Itsuo Takanami, Yasuhiro Oyama:
An Extreme Value Injection Approach with Reduced Learning Time to Make MLNs Multiple-Weight-Fault Tolerant. PRDC 2002: 301-310 - 2001
- [c18]Itsuo Takanami:
Built-in Self-Reconfiguring Systems for Fault Tolerant Mesh-Connected Processor Arrays by Direct Spare Replacement. DFT 2001: 134-142 - [c17]Tadayoshi Horita, Itsuo Takanami:
Analytical Results for Reconfiguration of E-11/2- Track Switch Torus Arrays with Multiple Fault Types. PRDC 2001: 233-240 - 2000
- [j59]Tadayoshi Horita, Itsuo Takanami:
Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions. IEEE Trans. Computers 49(6): 542-552 (2000) - [c16]Itsuo Takanami:
Built-in Self-Reconfiguring Systems for Mesh-Connected Processor Arrays with Spares on Two Rows/Columns. DFT 2000: 213-221 - [c15]Itsuo Takanami, Masaru Sato, Yun Ping Yang:
A Fault-Value Injection Approach for Multiple-Weight-Fault Tolerance of MNNs. IJCNN (3) 2000: 515-520 - [c14]Tadayoshi Horita, Itsuo Takanami:
A System for Efficiently Self-Reconstructing E-1½-Track Switch Torus Arrays. ISPAN 2000: 44-49 - [c13]Tadayoshi Horita, Itsuo Takanami:
A System for Efficiently Self-Reconstructing 1½-Track Switch Torus Arrays. PDPTA 2000
1990 – 1999
- 1999
- [c12]Tadayoshi Horita, Itsuo Takanami:
Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions. ISPAN 1999: 135-137 - 1997
- [c11]Takehiro Ito, Itsuo Takanami:
On fault injection approaches for fault tolerance of feedforward neural networks. Asian Test Symposium 1997: 88-93 - [c10]Itsuo Takanami, Tadayoshi Horita:
Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits. DFT 1997: 218-226 - [c9]Tadayoshi Horita, Itsuo Takanami:
A Polynomial Time Algorithm for Reconfiguring the 1 1/2 Track-Switch Model with PE and Bus faults. ISPAN 1997: 16-22 - [c8]Itsuo Takanami, Tadayoshi Horita:
A built-in self-reconfigurable scheme for 3D mesh arrays. ISPAN 1997: 458-464 - 1996
- [c7]Tadayoshi Horita, Itsuo Takanami:
Reconfiguration of 1 1/2 track-switch mesh-arrays with PE and bus faults. DFT 1996: 335- - 1995
- [j58]Akira Ito, Katsushi Inoue, Itsuo Takanami, Yue Wang:
The Effect of Inkdots for Two-Dimensional Automata. IJPRAI 9(5): 777-796 (1995) - [j57]Yue Wang, Katsushi Inoue, Itsuo Takanami:
Cooperating Systems of Three-Way, Two-Dimensional Finite Automata. IJPRAI 9(5): 797-811 (1995) - [j56]Akira Ito, Katsushi Inoue, Itsuo Takanami, Yue Wang:
Optimal Simulation of Two-Dimensional Alternating Finite Automata by Three-Way Nondeterministic Turing Machines. Theor. Comput. Sci. 143(1): 123-135 (1995) - [c6]Itsuo Takanami, Tadayoshi Horita:
Reconfigurable architectures for mesh-arrays with PE and link faults. DFT 1995: 108-116 - 1994
- [j55]Katsushi Inoue, Itsuo Takanami:
A Characterization of Recognizable Picture Languages. IJPRAI 8(2): 501-508 (1994) - [j54]Akira Ito, Katsushi Inoue, Itsuo Takanami, Yasuyoshi Inagaki:
Constant Leaf-Size Hierarchy of Two-Dimensional Alternating Turing Machines. IJPRAI 8(2): 509-524 (1994) - [j53]Makoto Sakamoto, Akira Ito, Katsushi Inoue, Itsuo Takanami:
Simulation of Three-Dimensional One-Marker Automata by Five-Way Turing Machines. Inf. Sci. 77(1-2): 77-99 (1994) - [j52]Katsushi Inoue, Akira Ito, Itsuo Takanami:
On 1-inkdot Alternating Turing Machines with Small Space. Theor. Comput. Sci. 127(1): 171-179 (1994) - 1993
- [j51]Katsushi Inoue, Akira Ito, Itsuo Takanami, Tsunehiro Yoshinaga:
A Note on Multi-Inkdot Nondeterministic Turing Machines with Small Space. Inf. Process. Lett. 48(6): 285-288 (1993) - [j50]Makoto Sakamoto, Katsushi Inoue, Itsuo Takanami:
A note on three-dimensional alternating Turing machines with space smaller than log m. Inf. Sci. 72(3): 225-249 (1993) - [j49]Itsuo Takanami, Katsushi Inoue, Takahiro Watanabe, Minoru Oka:
Construction of fault-tolerant mesh-connected highly parallel computer and its performance analysis. Systems and Computers in Japan 24(8): 11-24 (1993) - 1992
- [j48]Juraj Hromkovic, Katsushi Inoue, Branislav Rovan, Anna Slobodová, Itsuo Takanami, Klaus W. Wagner:
On the Power of One-Way Synchronized Alternating Machines with Small Space. Int. J. Found. Comput. Sci. 3(1): 65-79 (1992) - [j47]Katsushi Inoue, Itsuo Sakuramoto, Makoto Sakamoto, Itsuo Takanami:
Two Topics Concerning Two-Dimensional Automata Operating in Parallel. IJPRAI 6(2&3): 211-225 (1992) - [j46]Katsushi Inoue, Akira Ito, Itsuo Takanami:
A Relationship Between Nondeterministic Turing Machines and 1-Inkdot Turing Machines with Small Space. Inf. Process. Lett. 43(4): 225-227 (1992) - [c5]Katsushi Inoue, Itsuo Takanami:
A Characterization of Recognizable Picture Languages. ICPIA 1992: 133-143 - [c4]Akira Ito, Katsushi Inoue, Itsuo Takanami:
Constant Leaf-Size Hierarchy of Two-Dimensional Alternating Turing Machines. ICPIA 1992: 144-158 - 1991
- [j45]Katsushi Inoue, Akira Ito, Itsuo Takanami:
Alternating Turing Machines with Modified Accepting Structure. Int. J. Found. Comput. Sci. 2(4): 401-417 (1991) - [j44]Katsushi Inoue, Itsuo Takanami:
A survey of two-dimensional automata theory. Inf. Sci. 55(1-3): 99-121 (1991) - [j43]Katsushi Inoue, Akira Ito, Itsuo Takanami:
A Note on Real-Time One-Way Alternating Multicounter Machines. Theor. Comput. Sci. 88(2): 287-296 (1991) - 1990
- [j42]Katsushi Inoue, Itsuo Takanami, Akira Nakamura:
A note on time-bounded bottom-up pyramid cellular acceptors. Inf. Sci. 51(2): 121-133 (1990)
1980 – 1989
- 1989
- [j41]Akira Ito, Katsushi Inoue, Itsuo Takanami:
The Simulation of Two-Dimensional One-Marker Automata by Three-Way Turing Machines. IJPRAI 3(3-4): 393-404 (1989) - [j40]Juraj Hromkovic, Katsushi Inoue, Itsuo Takanami:
Lower Bounds for Language Recognition on Two-Dimensional Alternating Multihead Machines. J. Comput. Syst. Sci. 38(3): 431-451 (1989) - [j39]Hiroshi Taniguchi, Katsushi Inoue, Itsuo Takanami:
One-Dimensional Bounded Cellular Acceptor with Rotated Inputs. A Relationship between ∧ and ∨ Types. Systems and Computers in Japan 20(3): 1-12 (1989) - [j38]Akira Ito, Katsushi Inoue, Itsuo Takanami:
Deterministic Two-Dimensional On-Line Tessellation Acceptors are Equivalent to Two-Way Two-Dimensional Alternating Finite Automata Through 180°-Rotation. Theor. Comput. Sci. 66(3): 273-287 (1989) - [j37]Katsushi Inoue, Itsuo Takanami, Juraj Hromkovic:
A Leaf-Size Hierarchy of Two-Dimensional Alternating Turing Machines. Theor. Comput. Sci. 67(1): 99-110 (1989) - [p2]Akira Ito, Katsushi Inoue, Itsuo Takanami:
Complexity of Acceptance Problems for Two-Dimensional Automata. A Perspective in Theoretical Computer Science 1989: 70-94 - [p1]Akira Ito, Katsushi Inoue, Itsuo Takanami:
The Simulation of Two-Dimensional One-Marker Automata by Three-Way Turing Machines. Array Grammars, Patterns and Recognizers 1989: 115-126 - 1988
- [j36]Katsushi Inoue, Itsuo Takanami:
Some Considerations About NPRIORITY(1) Without ROM. Inf. Process. Lett. 28(4): 215-219 (1988) - [j35]Akira Ito, Katsushi Inoue, Itsuo Takanami:
A note on three-way two-dimensional alternating Turing machines. Inf. Sci. 45(1): 1-22 (1988) - [c3]
- [c2]Akira Ito, Katsushi Inoue, Itsuo Takanami:
The Simulation of Two-Dimensional One-Marker Automata by Three-Way Turing Machines. IMYCS 1988: 92-101 - 1987
- [j34]Hiroshi Taniguchi, Katsushi Inoue, Itsuo Takanami:
Hierarchical properties of the κ -neighborhood template A-type 2-dimensional bounded cellular acceptor. Systems and Computers in Japan 18(5): 79-90 (1987) - [j33]Hiroshi Taniguchi, Katsushi Inoue, Itsuo Takanami:
One-dimensional bounded cellular acceptor with rotated inputs. Systems and Computers in Japan 18(9): 52-63 (1987) - 1986
- [j32]Katsushi Inoue, Itsuo Takanami, Roland Vollmar:
Three-way two-dimensional finite automata with rotated inputs. Inf. Sci. 38(3): 271-282 (1986) - [j31]Akira Ito, Katsushi Inoue, Itsuo Takanami, Hiroshi Taniguchi:
Relationships of accepting powers between cellular space with bounded number of state-changes and other automata. Systems and Computers in Japan 17(7): 63-72 (1986) - [j30]Hiroshi Taniguchi, Katsushi Inoue, Itsuo Takanami, Shigeko Seki:
Relationship between the accepting powers of (k, l)-neighborhood template δ-type one-dimensional bounded cellular acceptors and other types of two-dimensional automata. Systems and Computers in Japan 17(9): 20-28 (1986) - 1985
- [j29]Katsushi Inoue, Akira Ito, Itsuo Takanami, Hiroshi Taniguchi:
A space-hierarchy result on two-dimensional alternating Turing machines with only universal states. Inf. Sci. 35(1): 79-90 (1985) - [j28]Hiroshi Matsuno, Katsushi Inoue, Hiroshi Taniguchi, Itsuo Takanami:
Alternating Simple Multihead Finite Automata. Theor. Comput. Sci. 36: 291-308 (1985) - [j27]Katsushi Inoue, Itsuo Takanami, Roland Vollmar:
Alternating On-Line Turing Machines with Only Universal States and Small Space Bounds. Theor. Comput. Sci. 41: 331-339 (1985) - 1984
- [j26]Katsushi Inoue, Itsuo Takanami, Akira Nakamura:
Connected pictures are not recognizable by deterministic two-dimensional on-line tessellation acceptors. Computer Vision, Graphics, and Image Processing 26(1): 126-129 (1984) - 1983
- [j25]Katsushi Inoue, Itsuo Takanami, Akira Nakamura:
Connected pictures are not recognizable by deterministic two-dimensional on-line tessellation acceptors. Computer Vision, Graphics, and Image Processing 22(2): 310-311 (1983) - [j24]Katsushi Inoue, Itsuo Takanami, Hiroshi Taniguchi:
Two-dimensional automata with rotated inputs (projection-type). Inf. Sci. 30(1): 11-36 (1983) - [j23]Manabu Toda, Katsushi Inoue, Itsuo Takanami:
Two-Dimensional Pattern Matching by Two-Dimensional on-Line Tessellation Acceptors. Theor. Comput. Sci. 24: 179-194 (1983) - [j22]Katsushi Inoue, Itsuo Takanami, Hiroshi Taniguchi:
A Relationship between Two-Dimensional Finite Automata and Three-Way Tape-Bounded Two-Dimensional Turing Machines. Theor. Comput. Sci. 24: 331-336 (1983) - [j21]Katsushi Inoue, Itsuo Takanami, Hiroshi Taniguchi:
Two-Dimensional Alternating Turing Machines. Theor. Comput. Sci. 27: 61-83 (1983) - 1982
- [j20]Akira Ito, Katsushi Inoue, Itsuo Takanami, Hiroshi Taniguchi:
Two-Dimensional Alternating Turing Machines with Only Universal States. Information and Control 55(1-3): 193-221 (1982) - [j19]Katsushi Inoue, Itsuo Takanami, Hiroshi Taniguchi:
A Note on Alternating On-Line Turing Machines. Inf. Process. Lett. 15(4): 164-168 (1982) - [j18]Hiroshi Taniguchi, Katsushi Inoue, Itsuo Takanami:
A note on three-dimensional finite automata. Inf. Sci. 26(1): 65-85 (1982) - [j17]Katsushi Inoue, Itsuo Takanami, Hiroshi Taniguchi:
A note on rebound automata. Inf. Sci. 26(1): 87-93 (1982) - [c1]Katsushi Inoue, Itsuo Takanami, Hiroshi Taniguchi:
Two-Dimensional Alternating Turing Machines. STOC 1982: 37-46 - 1980
- [j16]Katsushi Inoue, Itsuo Takanami:
A Note on Decision Problems for Three-Way Two-Dimensional Finite Automata. Inf. Process. Lett. 10(4/5): 245-248 (1980) - [j15]Katsushi Inoue, Itsuo Takanami:
A note on deterministic three-way tape-bounded two-dimensional Turing machines. Inf. Sci. 20(1): 41-55 (1980) - [j14]Katsushi Inoue, Itsuo Takanami, Hiroshi Taniguchi:
Two-dimensional automata with rotated inputs. Inf. Sci. 21(3): 221-240 (1980) - [j13]
- [j12]Katsushi Inoue, Itsuo Takanami, Akira Nakamura:
Nonclosure property of nondeterministic two-dimensional finite automata under cyclic closure. Inf. Sci. 22(1): 45-50 (1980)
1970 – 1979
- 1979
- [j11]Katsushi Inoue, Itsuo Takanami:
A Note on Cyclic Closure Operations. Inf. Process. Lett. 8(1): 15-16 (1979) - [j10]Katsushi Inoue, Itsuo Takanami:
A Note on Bottom-Up Pyramid Acceptors. Inf. Process. Lett. 8(1): 34-37 (1979) - [j9]Katsushi Inoue, Itsuo Takanami:
Three-way tape-bounded two-dimensional turing machines. Inf. Sci. 17(3): 195-220 (1979) - [j8]Katsushi Inoue, Itsuo Takanami:
On-line n-bounded multicounter automata. Inf. Sci. 17(3): 239-251 (1979) - [j7]Katsushi Inoue, Itsuo Takanami:
Closure properties of three-way and four-way tape-bounded two-dimensional turing machines. Inf. Sci. 18(3): 247-265 (1979) - [j6]Katsushi Inoue, Itsuo Takanami:
Three-way two-dimensional multicounter automata. Inf. Sci. 19(1): 1-20 (1979) - [j5]Katsushi Inoue, Itsuo Takanami, Akira Nakamura, Tadashi Ae:
One-Way Simple Multihead Finite Automata. Theor. Comput. Sci. 9: 311-328 (1979) - 1978
- [j4]Katsushi Inoue, Itsuo Takanami, Akira Nakamura:
A Note on Two-Dimensional Finite Automata. Inf. Process. Lett. 7(1): 49-52 (1978) - [j3]Katsushi Inoue, Itsuo Takanami:
A note on closure properties of the classes of sets accepted by tape-bounded two-dimensional turing machines. Inf. Sci. 15(2): 143-158 (1978) - [j2]Katsushi Inoue, Itsuo Takanami:
Cyclic closure properties of automata on a two-dimensional tape. Inf. Sci. 15(3): 229-242 (1978) - 1976
- [j1]Takao Asano, Michiro Shibui, Itsuo Takanami:
General Results on Tour Lengths in Machines and Digraphs. SIAM J. Comput. 5(4): 629-645 (1976)
Coauthor Index
[j58] [j57] [j56] [j55] [j54] [j53] [j52] [j51] [j50] [j49] [j48] [j47] [j46] [c5] [c4] [j45] [j44] [j43] [j42] [j41] [j40] [j39] [j38] [j37] [p2] [p1] [j36] [j35] [c3] [c2] [j34] [j33] [j32] [j31] [j30] [j29] [j28] [j27] [j26] [j25] [j24] [j23] [j22] [j21] [j20] [j19] [j18] [j17] [c1] [j16] [j15] [j14] [j13] [j12] [j11] [j10] [j9] [j8] [j7] [j6] [j5] [j4] [j3] [j2]
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