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 | 2013 | |
|---|---|---|
| c5 |      | Pei-Wen Luo, Chun Zhang, Yung-Tai Chang, Liang-Chia Cheng, Hung-Hsie Lee, Bih-Lan Sheu, Yu-Shih Su, Ding-Ming Kwai, Yiyu Shi: Benchmarking for research in power delivery networks of three-dimensional integrated circuits. ISPD 2013: 17-24 |
| 2012 | ||
| c4 | | Tao Wang, Pei-Wen Luo, Yu-Shih Su, Liang-Chia Cheng, Ding-Ming Kwai, Yiyu Shi: Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction. ASP-DAC 2012: 640-645 |
| 2011 | ||
| j3 | | Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska: Performance Optimization Using Variable-Latency Design Style. IEEE Trans. VLSI Syst. 19(10): 1874-1883 (2011) |
| c3 | | Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu Shi, Shih-Chieh Chang: Fault-tolerant 3D clock network. DAC 2011: 645-651 |
| 2010 | ||
| j2 | | Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang: Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers. IEEE Trans. on CAD of Integrated Circuits and Systems 29(12): 1921-1930 (2010) |
| 2009 | ||
| c2 | | Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang: Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. ICCAD 2009: 535-538 |
| 2008 | ||
| j1 | | Yu-Shih Su, Po-Hsien Chang, Shih-Chieh Chang, TingTing Hwang: Synthesis of a novel timing-error detection architecture. ACM Trans. Design Autom. Electr. Syst. 13(1) (2008) |
| 2007 | ||
| c1 | | Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska: An Efficient Mechanism for Performance Optimization of Variable-Latency Designs. DAC 2007: 976-981 |
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