| 2013 | ||
|---|---|---|
| b1 | Vytautas Stuikys, Robertas Damasevicius: Meta-Programming and Model-Driven Meta-Program Development - Principles, Processes and Techniques. Advanced information and knowledge processing, Springer 2013, isbn 978-1-4471-4125-9, pp. I-XVII, 1-326 | |
| 2012 | ||
| c12 | Paulius Paskevicius, Robertas Damasevicius, Vytautas Stuikys: Change Impact Analysis of Feature Models. ICIST 2012: 108-122 | |
| c11 | Vytautas Stuikys, Kristina Bespalova: Methodology and Experiments to Transform Heterogeneous Meta-program into Meta-meta-programs. ICIST 2012: 210-225 | |
| c10 | Paulius Paskevicius, Robertas Damasevicius, Vytautas Stuikys: Quality-Oriented Product Line Modeling Using Feature Diagrams and Preference Logic. ICIST 2012: 241-254 | |
| c9 | ||
| 2010 | ||
| j12 | Robertas Damasevicius, Vytautas Stuikys: Metrics for evaluation of metaprogram complexity. Comput. Sci. Inf. Syst. 7(4): 769-787 (2010) | |
| 2009 | ||
| j11 | Vytautas Stuikys, Ilona Brauklyte: Aggregating of Learning Object Units Derived from a Generative Learning Object. Informatics in Education 8(2): 295-314 (2009) | |
| c8 | Robertas Damasevicius, Vytautas Stuikys: Specification and Generation of Learning Object Sequences for E-learning Using Sequence Feature Diagrams and Metaprogramming Techniques. ICALT 2009: 572-576 | |
| 2008 | ||
| j10 | Vytautas Stuikys, Robertas Damasevicius: Development of Generative Learning Objects Using Feature Diagrams and Generative Techniques. Informatics in Education 7(2): 277-288 (2008) | |
| c7 | Robertas Damasevicius, Vytautas Stuikys, Jevgenijus Toldinas: Domain Ontology-Based Generative Component Design Using Feature Diagrams and Meta-programming Techniques. ECSA 2008: 338-341 | |
| c6 | Virginija Limanauskiene, Galina Romanova, Vjaceslavs Sitikovs, Vytautas Stuikys: Network of Schools as a General Framework for Validation of the UNITE Project Outcomes. ICALT 2008: 669-670 | |
| c5 | Robertas Damasevicius, Vytautas Stuikys: On the Technological Aspects of Generative Learning Object Development. ISSEP 2008: 337-348 | |
| 2007 | ||
| j9 | Robertas Damasevicius, Vytautas Stuikys: Estimation of Power Consumption at Behavioral Modeling Level Using SystemC. EURASIP J. Emb. Sys. 2007 (2007) | |
| 2004 | ||
| j8 | Vytautas Stuikys, Robertas Damasevicius: Soft IP Customisation Model Based on Metaprogramming Techniques. Informatica, Lith. Acad. Sci. 15(1): 111-126 (2004) | |
| j7 | Robertas Damasevicius, Vytautas Stuikys: Application of the object-oriented principles for hardware and embedded system design. Integration 38(2): 309-339 (2004) | |
| c4 | Robertas Damasevicius, Vytautas Stuikys: Application of UML for hardware design based on design process model. ASP-DAC 2004: 244-249 | |
| 2003 | ||
| j6 | Robertas Damasevicius, Vytautas Stuikys: Wrapping of Soft IPs for Interface-based Design Using Heterogeneous Metaprogramming. Informatica, Lith. Acad. Sci. 14(1): 3-18 (2003) | |
| c3 | Robertas Damasevicius, Giedrius Majauskas, Vytautas Stuikys: Application of design patterns for hardware design. DAC 2003: 48-53 | |
| 2002 | ||
| j5 | Vytautas Stuikys, Robertas Damasevicius: Relationship Model of Abstractions Used for Developing Domain Generators. Informatica, Lith. Acad. Sci. 13(1): 111-128 (2002) | |
| j4 | Robertas Damasevicius, Vytautas Stuikys: Separation Of Concerns in Multi-language Specifications. Informatica, Lith. Acad. Sci. 13(3): 255-274 (2002) | |
| c2 | Vytautas Stuikys, Robertas Damasevicius, Giedrius Ziberkas, Giedrius Majauskas: Soft IP Design Framework Using Metaprogramming Techniques. DIPES 2002: 257-266 | |
| 2001 | ||
| c1 | Vytautas Stuikys, Giedrius Ziberkas, Robertas Damasevicius, Giedrius Majauskas: Two approaches for developing generic components in VHDL. DATE 2001: 800 | |
| 2000 | ||
| j3 | Vytautas Stuikys, Robertas Damasevicius: Scripting Language Open PROMOL and its Processor. Informatica, Lith. Acad. Sci. 11(1): 71-86 (2000) | |
| j2 | Vytautas Stuikys, Giedrius Ziberkas, Robertas Damasevicius: The Language-Centric Program Generator Models: 3L Paradigm. Informatica, Lith. Acad. Sci. 11(3): 325-348 (2000) | |
| 1998 | ||
| j1 | Vytautas Stuikys: Design of Reusable VHDL Component Using External Functions. Informatica, Lith. Acad. Sci. 9(4): 491-506 (1998) | |
Colors in the list of coauthors
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