Luca Sterpone

Luca Cassano, Dario Cozzi, Sebastian Korf, Jens Hagemeyer, Mario Porrmann, Luca Sterpone: On-line testing of permanent radiation effects in reconfigurable systems. DATE 2013: 717-720

Jens Hagemeyer, Arne Hilgenstein, Dirk Jungewelter, Dario Cozzi, Carmelo Felicetti, Ulrich Rückert, Sebastian Korf, Markus Koester, Fabio Margaglia, Mario Porrmann, Florian Dittmann, Michael Ditze, Julian Harris, Luca Sterpone, Jorgen Ilstad: A scalable platform for run-time reconfigurable satellite payload processing. AHS 2012: 9-16

Davide Sabena, Matteo Sonza Reorda, Luca Sterpone: A new SBST algorithm for testing the register file of VLIW processors. DATE 2012: 412-417

Davide Sabena, Matteo Sonza Reorda, Luca Sterpone: On the development of Software-Based Self-Test methods for VLIW processors. DFT 2012: 25-30

Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone: Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs. DFT 2012: 115-120

Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Marco Ottavi, Salvatore Pontarelli, Adelio Salsano, Cecilia Metra, Martin Omaña, Daniele Rossi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Simone Gerardin, M. Bagatin, Alessandro Paccagnella: High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies. DFT 2012: 121-125

Luca Sterpone, Davide Sabena, Matteo Sonza Reorda: A New Fault Injection Approach for Testing Network-on-Chips. PDP 2012: 530-535

Davide Sabena, Matteo Sonza Reorda, Luca Sterpone: On the optimized generation of Software-Based Self-Test programs for VLIW processors. VLSI-SoC 2012: 129-134

Niccolò Battezzati, Luca Sterpone, Massimo Violante: Reconfigurable Field Programmable Gate Arrays for Mission-Critical Applications. Springer 2011, isbn 978-1-4419-7594-2, pp. I-VII, 1-220

Hipólito Guzmán-Miranda, Luca Sterpone, Massimo Violante, Miguel A. Aguirre, Manuel Gutiérrez-Rizo: Coping With the Obsolescence of Safety- or Mission-Critical Embedded Systems Using FPGAs. IEEE Transactions on Industrial Electronics 58(3): 814-821 (2011)

Luca Sterpone, Fabio Margaglia, Markus Köster, Jens Hagemeyer, Mario Porrmann: Analysis of SEU effects in partially reconfigurable SoPCs. AHS 2011: 129-136

Luca Sterpone, Luigi Carro, Debora Matos, Stephan Wong, F. Fakhar: A new reconfigurable clock-gating technique for low power SRAM-based FPGAs. DATE 2011: 752-757

Luca Sterpone, Davide Sabena, Salvatore Campagna, Matteo Sonza Reorda: Fault injection analysis of transient faults in clustered VLIW processors. DDECS 2011: 207-212

Jorge Luis Lagos-Benites, Michelangelo Grosso, Luca Sterpone, Matteo Sonza Reorda, G. Audisio, M. Pipponzi, Marco Sabatini: A Low-Cost Emulation System for Fast Co-verification and Debug. European Test Symposium 2011: 212

Luca Sterpone: A New Timing Driven Placement Algorithm for Dependable Circuits on SRAM-based FPGAs. TRETS 4(1): 7 (2010)

Luca Sterpone, Niccolò Battezzati: A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs. DATE 2010: 1231-1236

Luca Sterpone, Niccolò Battezzati: On the mitigation of SET broadening effects in integrated circuits. DDECS 2010: 36-39

Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Niccolò Battezzati, Luca Sterpone, Massimo Violante: An integrated flow for the design of hardened circuits on SRAM-based FPGAs. European Test Symposium 2010: 214-219

M. Di Marzio, Michelangelo Grosso, Matteo Sonza Reorda, Luca Sterpone, G. Audisio, Marco Sabatini: A novel scalable and reconfigurable emulation platform for embedded systems verification. ISCAS 2010: 865-868

Niccolò Battezzati, Luca Sterpone, Massimo Violante, Filomena Decuzzi: A new software tool for static analysis of SET sensitiveness in Flash-based FPGAs. VLSI-SoC 2010: 79-84

Luca Sterpone: Electronics System Design Techniques for Safety Critical Applications. Lecture Notes in Electrical Engineering 26, Springer 2009, isbn 978-1-4020-8979-7

Luca Sterpone: A Novel Dual-Core Architecture for the Analysis of DNA Microarray Images. IEEE T. Instrumentation and Measurement 58(8): 2653-2662 (2009)

Luca Sterpone: Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs. ARC 2009: 85-96

Francesco Abate, Luca Sterpone, Massimo Violante, Fernanda Lima Kastensmidt: A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs. DATE 2009: 1226-1229

Niccolò Battezzati, Filomena Decuzzi, Luca Sterpone, Massimo Violante: Soft errors in Flash-based FPGAs: Analysis methodologies and first results. FPL 2009: 723-724

Eduardo Luis Rhod, Luca Sterpone, Luigi Carro: A new RC design for mixed-grain based dynamically reconfigurable architectures. ICECS 2009: 984-987

Cristiana Bolchini, Antonio Miele, Fabio Rebaudengo, Fabio Salice, Donatella Sciuto, Luca Sterpone, Massimo Violante: Software and Hardware Techniques for SEU Detection in IP Processors. J. Electronic Testing 24(1-3): 35-44 (2008)

Luca Sterpone, Niccolò Battezzati: A Novel Design Flow for the Performance Optimization of Fault Tolerant Circuits on SRAM-based FPGA's. AHS 2008: 157-163

Alfredo Benso, Stefano Di Carlo, Gianfranco Politano, Luca Sterpone: Differential gene expression graphs: A data structure for classification in DNA microarrays. BIBE 2008: 1-6

Alfredo Benso, Stefano Di Carlo, Gianfranco Politano, Luca Sterpone: A graph-based representation of Gene Expression profiles in DNA microarrays. CIBCB 2008: 75-82

Luca Sterpone, M. A. Aguirre, Jonathan Noel Tombs, Hipólito Guzmán-Miranda: On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications. DATE 2008: 336-341

Niccolò Battezzati, Simone Gerardin, Andrea Manuzzato, Alessandro Paccagnella, Sana Rezgui, Luca Sterpone, Massimo Violante: On the Evaluation of Radiation-Induced Transient Faults in Flash-Based FPGAs. IOLTS 2008: 135-140

Luca Sterpone: FPGA PAL Design Tools. Wiley Encyclopedia of Computer Science and Engineering 2008

Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro: Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs. J. Electronic Testing 23(1): 47-54 (2007)

Oscar Ruano, Pilar Reyes, Juan Antonio Maestro, Luca Sterpone, Pedro Reviriego: An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques. DDECS 2007: 261-266

Andrea Manuzzato, Paolo Rech, Simone Gerardin, Alessandro Paccagnella, Luca Sterpone, Massimo Violante: Sensitivity Evaluation of TMR-Hardened Circuits to Multiple SEUs Induced by Alpha Particles in Commercial SRAM-Based FPGAs. DFT 2007: 79-86

Salvatore Pontarelli, Luca Sterpone, Gian-Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante: Optimization of Self Checking FIR filters by means of Fault Injection Analysis. DFT 2007: 96-104

Luca Sterpone, Massimo Violante: Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs. European Test Symposium 2007: 159-164

Luca Sterpone, Massimo Violante: A new decompression system for the configuration process of SRAM-based FPGAS. ACM Great Lakes Symposium on VLSI 2007: 241-246

Luca Sterpone, Massimo Violante: A new hardware architecture for performing the gridding of DNA microarray images. ACM Great Lakes Symposium on VLSI 2007: 341-346

Salvatore Pontarelli, Luca Sterpone, Gian-Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante: Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders. IOLTS 2007: 194-196

Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda: On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs. CoRR abs/0710.4688 (2007)

Luca Sterpone, Massimo Violante: Hardening FPGA-based Systems Against SEUs: A New Design Methodology. JCP 1(1): 22-30 (2006)

Luca Sterpone, Massimo Violante: A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs. IEEE Trans. Computers 55(6): 732-744 (2006)

Maurizio Martina, Guido Masera, Andrea Molino, Fabrizio Vacca, Luca Sterpone, Massimo Violante: A new approach to compress the configuration information of programmable devices. DATE Designers' Forum 2006: 48-51

Luca Sterpone, Massimo Violante: ReCoM: A New Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications. DDECS 2006: 54-58

Maurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto: Combined software and hardware techniques for the design of reliable IP processors. DFT 2006: 265-273

Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena: Fault Injection-based Reliability Evaluation of SoPCs. European Test Symposium 2006: 75-82

Luca Sterpone, Massimo Violante: Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices. IOLTS 2006: 189-190

Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda: On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs. DATE 2005: 1290-1295

Luca Sterpone, Massimo Violante: A design flow for protecting FPGA-based systems against single event upsets. DFT 2005: 436-444

Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero, Luca Sterpone, Massimo Violante: New evolutionary techniques for test-program generation for complex microprocessor cores. GECCO 2005: 2193-2194

Matteo Sonza Reorda, Luca Sterpone, Massimo Violante: Efficient Estimation of SEU Effects in SRAM-Based FPGAs. IOLTS 2005: 54-59

Paolo Bernardi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante: On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs. IOLTS 2004: 115-120