Costas J. Spanos

Lerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He: Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability. IEEE Trans. on CAD of Integrated Circuits and Systems 30(3): 388-401 (2011)

Borivoje Nikolic, Ji-Hoon Park, Jaehwa Kwak, Bastien Giraud, Zheng Guo, Liang-Teck Pang, Seng Oon Toh, Ruzica Jevtic, Kun Qian, Costas J. Spanos: Technology Variability From a Design Perspective. IEEE Trans. on Circuits and Systems 58-I(9): 1996-2009 (2011)

Qian Ying Tang, Costas J. Spanos: Non-Gaussian uncertainty propagation in statistical circuit simulation. ISQED 2011: 417-424

Yu Ben, Costas J. Spanos: Estimating the probability density function of critical path delay via partial least squares dimension reduction. ISQED 2011: 721-727

Yu Ben, Laurent El Ghaoui, Kameshwar Poolla, Costas J. Spanos: Yield-constrained digital circuit sizing via sequential geometric programming. ISQED 2010: 114-121

Lerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He: Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability. DAC 2009: 104-109

Paul Friedberg, Yu Cao, Jason Cain, Ruth Wang, Jan M. Rabaey, Costas J. Spanos: Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization. ISQED 2005: 516-521

Costas J. Spanos, Stephen W. Director: Parameter Extraction for Statistical IC Process Characterization. IEEE Trans. on CAD of Integrated Circuits and Systems 5(1): 66-78 (1986)