Balaram Sinharoy

Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban: POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. J. Solid-State Circuits 46(1): 145-161 (2011)

Ronald N. Kalla, Balaram Sinharoy, William J. Starke, Michael S. Floyd: Power7: IBM's Next-Generation Server Processor. IEEE Micro 30(2): 7-15 (2010)

Dieter F. Wendel, Ronald N. Kalla, Robert Cargnoni, Joachim G. Clabes, Joshua Friedrich, R. Frech, James A. Kahle, Balaram Sinharoy, William J. Starke, Scott Taylor, Steve Weitzel, Sam G. Chu, Md. Saiful Islam, Victor V. Zyuban: The implementation of POWER7^TM: A highly parallel and scalable multi-core high-end server processor. ISSCC 2010: 102-103

Balaram Sinharoy: POWER7 multi-core processor design. MICRO 2009: 1

Balaram Sinharoy, Ronald N. Kalla, Joel M. Tendler, Richard J. Eickemeyer, Jody B. Joyner: POWER5 system microarchitecture. IBM Journal of Research and Development 49(4-5): 505-522 (2005)

Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler: Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. HPCA 2005: 238-242

Ronald N. Kalla, Balaram Sinharoy, Joel M. Tendler: IBM Power5 Chip: A Dual-Core Multithreaded Processor. IEEE Micro 24(2): 40-47 (2004)

Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam G. Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip Restle, Ronald N. Kalla, Joseph McGill, J. Steve Dodson: Design and implementation of the POWER5 microprocessor. DAC 2004: 670-672

Joel M. Tendler, J. Steve Dodson, J. S. Fields Jr., Hung Le, Balaram Sinharoy: POWER4 system microarchitecture. IBM Journal of Research and Development 46(1): 5-26 (2002)

Wael El-Essawy, David H. Albonesi, Balaram Sinharoy: A microarchitectural-level step-power analysis tool. ISLPED 2002: 263-266

Balaram Sinharoy: Compiler optimization to improve data locality for processor multithreading. Scientific Programming 7(1): 21-37 (1999)

Balaram Sinharoy: Optimized Thread Creation for Processor Multithreading. Comput. J. 40(6): 388-400 (1997)

Balaram Sinharoy, Boleslaw K. Szymanski: Introduction: Special Issue on Optimising Compilers for Parallel Languages. Parallel Algorithms Appl. 12(1-3): 1-4 (1997)

Balaram Sinharoy, Boleslaw K. Szymanski: Parallelising Compilers and Systems. Parallel Algorithms Appl. 12(1-3): 5-20 (1997)

Balaram Sinharoy, Rama Govindaraju: Improving Software MP Efficiency for Shared Memory Systems. HICSS (1) 1996: 111-120

Balaram Sinharoy, Boleslaw K. Szymanski: Announcement of a Special Issue of the Journal of Parallel Algorithms and Applications on Optimising Compilers for Parallel Languages. Parallel Algorithms Appl. 7(3-4): 313 (1995)

Boleslaw K. Szymanski, William Maniatty, Balaram Sinharoy: Simultaneous Parallel Reduction on SIMD Machines. Parallel Processing Letters 5: 437-449 (1995)

Balaram Sinharoy, Boleslaw K. Szymanski: Data and Task Alignment in Distributed Memory Architectures. J. Parallel Distrib. Comput. 21(1): 61-74 (1994)

Balaram Sinharoy, Boleslaw K. Szymanski: Finding Optimum Wavefront of Parallel Computation. Parallel Algorithms Appl. 2(1-2): 5-26 (1994)

Can C. Özturan, Balaram Sinharoy, Boleslaw K. Szymanski: Compiler Technology for Parallel Scientific Computation. Scientific Programming 3(3): 201-225 (1994)

Boleslaw K. Szymanski, Balaram Sinharoy: Complexity of the Closest Vector Problem in a Lattice Generated by (0, 1)-Matrix. Inf. Process. Lett. 42(3): 121-126 (1992)

Boleslaw K. Szymanski, Balaram Sinharoy: Corrigenda: Complexity of the Closest Vector Problem in a Lattice Generated by (0, 1)-Matrix. Inf. Process. Lett. 43(3): 167 (1992)

William Maniatty, Boleslaw K. Szymanski, Balaram Sinharoy: Efficiency of Data Alignment on Maspar. SIGPLAN Workshop 1992: 48-51