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 | 2012 | |
|---|---|---|
| c10 |      | Umair F. Siddiqi, Yoichi Shiraishi, Mona Abo El Dahb, Sadiq M. Sait: Finding Multi-Objective Shortest Paths Using Memory-Efficient Stochastic Evolution Based Algorithm. ICNC 2012: 182-187 |
| 2011 | ||
| c9 | | Umair F. Siddiqi, Yoichi Shiraishi, Mona Abo El Dahb, Sadiq M. Sait: Simulated Evolution (SimE) Based Embedded System Synthesis Algorithm for Electric Circuit Units (ECUs). ICANNGA (1) 2011: 400-409 |
| c8 | | Umair Farooq Siddiqi, Yoichi Shiraishi, Sadiq M. Sait: Multi-constrained route optimization for Electric Vehicles (EVs) using Particle Swarm Optimization (PSO). ISDA 2011: 391-396 |
| c7 | | Umair F. Siddiqi, Yoichi Shiraishi, Sadiq M. Sait: Multi constrained Route Optimization for Electric Vehicles using SimE. SoCPaR 2011: 376-383 |
| 2009 | ||
| c6 | | Yoichi Shiraishi, Takaaki Ono, Mona Abo El Dahb: Solution Space Reduction of Simulated Evolution Algorithm for Solving Standard Cell Placement Problem. ICNC (4) 2009: 420-424 |
| 2001 | ||
| c5 | | Jie Zhou, Yoichi Shiraishi, Ushio Yamamoto, Yoshikuni Onozato: Dynamic Allocation of Transmitter Power in a DS-CDMA Cellular System Using Genetic Algorithms. ICN (1) 2001: 579-588 |
| 1993 | ||
| c4 | | Masato Mogaki, Yoichi Shiraishi, Mitsuyuki Kimura, Tetsuro Hino: Cooperative Approach to a Practical Analog LSI Layout System. DAC 1993: 544-549 |
| 1991 | ||
| j2 | | Yoichi Shiraishi, Jun'ya Sakemi, Kazuyuki Fukuda: Optimality of a feedthrough assignment algorithm in a CMOS logic cell layout. IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 982-993 (1991) |
| 1990 | ||
| c3 |  | Yoichi Shiraishi, Mitsuyuki Kimura, Kazuhiko Kobayashi, Tetsuro Hino, Miki Seriuchi, Manabu Kusaoke: A High-Packing Density Module Generator for Bipolar Analog LSIs. ICCAD 1990: 194-197 |
| 1988 | ||
| c2 | | Yoichi Shiraishi, Jun'ya Sakemi, Makoto Kutsuwada, Akira Tsukizoe, Takashi Satoh: A High Packing Density Module Generator for CMOS Logic Cells. DAC 1988: 439-444 |
| 1987 | ||
| j1 | | Yoichi Shiraishi, Jun'ya Sakemi: A Permeation Router. IEEE Trans. on CAD of Integrated Circuits and Systems 6(3): 462-471 (1987) |
| 1986 | ||
| c1 | | Yasushi Ogawa, Tatsuki Ishii, Yoichi Shiraishi, Hidekazu Terai, Tokinori Kozawa, Kyoji Yuyama, Kyoji Chiba: Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs. DAC 1986: 404-410 |
Colors in the list of coauthors
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