Rupesh S. Shelar

Rupesh S. Shelar: A Fast and Near-Optimal Clustering Algorithm for Low-Power Clock Tree Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 31(11): 1781-1786 (2012)

Yifang Liu, Rupesh S. Shelar, Jiang Hu: Simultaneous Technology Mapping and Placement for Delay Minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 30(3): 416-426 (2011)

Rupesh S. Shelar: Routing With Constraints for Post-Grid Clock Distribution in Microprocessors. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 245-249 (2010)

Rupesh S. Shelar, Marek Patyra: Impact of local interconnects on timing and power in a high performance microprocessor. ISPD 2010: 145-152

Rupesh S. Shelar: An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors. ISPD 2009: 141-148

Yifang Liu, Rupesh S. Shelar, Jiang Hu: Delay-optimal simultaneous technology mapping and placement with applications to timing optimization. ICCAD 2008: 101-106

Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar: Routing Congestion in VLSI Circuits - Estimation and Optimization. Series on integrated circuits and systems, Springer 2007, isbn 978-0-387-30037-5, pp. I-XIV, 1-248

Rupesh S. Shelar: An efficent clustering algorithm for low power clock tree synthesis. ISPD 2007: 181-188

Rupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar: Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 625-636 (2006)

Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang: A predictive distributed congestion metric with application to technology mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 696-710 (2005)

Rupesh S. Shelar, Sachin S. Sapatnekar: BDD decomposition for delay oriented pass transistor logic synthesis. IEEE Trans. VLSI Syst. 13(8): 957-970 (2005)

Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar: An efficient technology mapping algorithm targeting routing congestion under delay constraints. ISPD 2005: 137-144

Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang: A predictive distributed congestion metric and its application to technology mapping. ISPD 2004: 210-217

Rupesh S. Shelar, Sachin S. Sapatnekar: Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits. IWLS 2002: 209-214

Rupesh S. Shelar, Sachin S. Sapatnekar: An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. VLSI Design 2002: 87-92

Rupesh S. Shelar, Sachin S. Sapatnekar: Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits. ICCAD 2001: 449-452

Rupesh S. Shelar, Sacheendra Nath, Jagmohan S. Nanaware: Parameterized Reusable Component Library Methodology. EUROMICRO 2000: 1410-1415

Rupesh S. Shelar, Madhav P. Desai, H. Narayanan: Decomposition of Finite State Machines for Area, Delay Minimization. ICCD 1999: 620-625