Jaume Segura

Víctor H. Champac, Julio Vazquez Hernandez, Salvador Barcelo, Roberto Gómez, Chuck Hawkins, Jaume Segura: Testing of Stuck-Open Faults in Nanometer Technologies. IEEE Design & Test of Computers 29(4): 80-91 (2012)

Hector Villacorta, Víctor H. Champac, Sebastiàn A. Bota, Jaume Segura: Resistive bridge defect detection enhancement under parameter variations combining Low V_DD and body bias in a delay based test. Microelectronics Reliability 52(11): 2799-2804 (2012)

Bartomeu Alorda, Gabriel Torrens, Sebastiàn A. Bota, Jaume Segura: 8T vs. 6T SRAM cell radiation robustness: A comparative analysis. Microelectronics Reliability 51(2): 350-359 (2011)

Bartomeu Alorda, Gabriel Torrens, Sebastiàn A. Bota, Jaume Segura: Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation. DATE 2011: 986-991

Salvador Barcelo, X. Gili, Sebastiàn A. Bota, Jaume Segura: An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computation. DATE 2011: 1602-1607

Gabriel Torrens, Bartomeu Alorda, Salvador Barcelo, José Luis Rosselló, Sebastiàn A. Bota, Jaume Segura: Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination. IEEE Trans. on Circuits and Systems 57-II(4): 280-284 (2010)

Bartomeu Alorda, Gabriel Torrens, Sebastiàn A. Bota, Jaume Segura: Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs. DATE 2010: 429-434

Sebastiàn A. Bota, Gabriel Torrens, Bartomeu Alorda, J. Verd, Jaume Segura: Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories. IOLTS 2010: 141-146

Jaume Segura, Vicente R. Tomás López, Arturo Sáez Esteve, Juan J. Martínez: Automated agent-based system for weather information. EATIS 2009: 15

Julio César Vázquez, Víctor H. Champac, Chuck Hawkins, Jaume Segura: Stuck-Open Fault Leakage and Testing in Nanometer Technologies. VTS 2009: 315-320

José Luis Rosselló, Vincent Canals, Ivan de Paúl, Jaume Segura: Using stochastic logic for efficient pattern recognition analysis. IJCNN 2008: 1057-1061

Bartomeu Alorda, Ivan de Paúl, Jaume Segura: Charge-based testing BIST for embedded memories. IET Computers & Digital Techniques 1(5): 481-490 (2007)

José Luis Rosselló, Carol de Benito, Sebastiàn A. Bota, Jaume Segura: Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs. DATE 2007: 1271-1276

X. Cano, Sebastiàn A. Bota, R. Graciani, David Gascon, A. Herms, A. Comerma, Jaume Segura, Lluís Garrido: Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics Experiment. IOLTS 2007: 183-184

Sebastiàn A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura: Smart Temperature Sensor for Thermal Testing of Cell-Based ICs. CoRR abs/0710.4733 (2007)

José Luis Rosselló, Vicens Canals, Sebastiàn A. Bota, Ali Keshavarzi, Jaume Segura: A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. CoRR abs/0710.4759 (2007)

Sebastiàn A. Bota, José Luis Rosselló, Carol de Benito, Ali Keshavarzi, Jaume Segura: Impact of Thermal Gradients on Clock Skew and Testing. IEEE Design & Test of Computers 23(5): 414-424 (2006)

José Luis Rosselló, Jaume Segura: A compact model to identify delay faults due to crosstalk. DATE 2006: 902-906

Jaume Segura: CMOS Testing at the End of the Roadmap: Challenges and Opportunities. DDECS 2006: 2

José Luis Rosselló, Sebastiàn A. Bota, Vicens Canals, Ivan de Paúl, Jaume Segura: A Fully CMOS Low-Cost Chaotic Neural Network. IJCNN 2006: 659-663

José Luis Rosselló, Carol de Benito, Sebastiàn A. Bota, Jaume Segura: Leakage Power Characterization Considering Process Variations. PATMOS 2006: 66-74

Sebastiàn A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura: Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?. VTS 2006: 358-363

José Luis Rosselló, Vicens Canals, Sebastiàn A. Bota, Ali Keshavarzi, Jaume Segura: A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. DATE 2005: 206-211

Sebastiàn A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura: Smart Temperature Sensor for Thermal Testing of Cell-Based ICs. DATE 2005: 464-465

Bartomeu Alorda, Sebastiàn A. Bota, Jaume Segura: A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits. IOLTS 2005: 177-182

José Luis Rosselló, Sebastiàn A. Bota, Jaume Segura: Compact Static Power Model of Complex CMOS Gates. PATMOS 2005: 348-354

Bartomeu Alorda, Vincent Canals, Jaume Segura: A Two-Level Power-Grid Model for Transient Current Testing Evaluation. J. Electronic Testing 20(5): 543-552 (2004)

José Luis Rosselló, Jaume Segura: A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk. DATE 2004: 954-961

Bartomeu Alorda, Vicens Canals, Ivan de Paúl, Jaume Segura: A BIST-based Charge Analysis for Embedded Memories. IOLTS 2004: 199-206

Sebastiàn A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura, Ali Keshavarzi: Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism. ITC 2004: 1276-1284

Joan Font, J. Ginard, Rodrigo Picos, Eugeni Isern, Jaume Segura, Miquel Roca, Eugenio García: A BICS for CMOS OpAmps by Monitoring the Supply Current Peak. J. Electronic Testing 19(5): 597-603 (2003)

Charles F. Hawkins, Ali Keshavarzi, Jaume Segura: A View from the Bottom: Nanometer Technology AC Parametric Failures -- Why, Where, and How to Detect. DFT 2003: 267-

Bartomeu Alorda, Jaume Segura: An Evaluation of Built-in vs. Off-chip Strategies for On-line Transient Current Testing. IOLTS 2003: 178-182

Bartomeu Alorda, B. Bloechel, Ali Keshavarzi, Jaume Segura: CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing. ITC 2003: 719-726

José Luis Rosselló, Jaume Segura: A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates. PATMOS 2003: 51-59

Jaume Segura, Peter C. Maxwell: Guest Editors' Introduction: Defect-Oriented Testing in the Deep-Submicron Era. IEEE Design & Test of Computers 19(5): 5-7 (2002)

José Luis Rosselló, Jaume Segura: Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers. IEEE Trans. on CAD of Integrated Circuits and Systems 21(4): 433-448 (2002)

Swarup Bhunia, Kaushik Roy, Jaume Segura: A novel wavelet transform based transient current analysis for fault detection and localization. DAC 2002: 361-366

Joan Font, J. Ginard, Eugeni Isern, Miquel Roca, Jaume Segura, Eugenio García: A BICS for CMOS Opamps by Monitoring the Supply Current Peak. IOLTW 2002: 94-98

Bartomeu Alorda, André Ivanov, Jaume Segura: An Off-Chip Sensor Circuit for On-Line Transient Current Testing. IOLTW 2002: 192

Jaume Segura, Ali Keshavarzi, Jerry M. Soden, Charles F. Hawkins: Parametric Failures in CMOS ICs - A Defect-Based Analysis. ITC 2002: 90-99

Bartomeu Alorda, M. Rosales, Jerry M. Soden, Charles F. Hawkins, Jaume Segura: Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMs. ITC 2002: 947-953

Chuck Hawkins, Jaume Segura: GHz Testing and Its Fuzzy Targets. ITC 2002: 1228

José Luis Rosselló, Jaume Segura: A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers. PATMOS 2002: 219-228

Jaume Segura, Vivek De, Ali Keshavarzi: Challenges in Nanometric Technology Scaling: Trends and Projections. VTS 2002: 447-448

José Luis Rosselló, Jaume Segura: Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization. ICCAD 2001: 494-

Ivan de Paúl, M. Rosales, Bartomeu Alorda, Jaume Segura, Charles F. Hawkins, Jerry M. Soden: Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments. VTS 2001: 286-291

Rodrigo Picos, Miquel Roca, Eugeni Isern, Jaume Segura, Eugeni García-Moreno: Experimental Results on BIC Sensors for Transient Current Testing. J. Electronic Testing 16(3): 235-241 (2000)

Bartomeu Alorda, Ivan de Paúl, Jaume Segura, T. Miller: On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor. IOLTW 2000: 87-91

Charles F. Hawkins, Jaume Segura: Test and Reliability: Partners in IC Manufacturing, Part 1. IEEE Design & Test of Computers 16(3): 64-71 (1999)

Charles F. Hawkins, Jaume Segura, Jerry M. Soden, Ted Dellin: Test and Reliability: Partners in IC Manufacturing, Part 2. IEEE Design & Test of Computers 16(4): 66-73 (1999)

Eugeni Isern, Miquel Roca, Jaume Segura: Analyzing the Need for ATPG Targeting GOS Defects. VTS 1999: 420-425

Eugeni García-Moreno, Benjamín Iñíguez, Miquel Roca, Jaume Segura, Eugeni Isern: Clocked Dosimeter Compatible with Digital CMOS Technology. J. Electronic Testing 12(1-2): 101-110 (1998)

Jaume Segura, Carol de Benito, A. Rubio, Charles F. Hawkins: A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors. J. Electronic Testing 8(3): 229-239 (1996)

Jaume Segura, Carol de Benito, A. Rubio, Charles F. Hawkins: A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level. ITC 1995: 544-551