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Julien Schmaltz
2010 – today
- 2013
[c28]Freek Verbeek, Sebastiaan J. C. Joosten, Julien Schmaltz: Formal Deadlock Verification for Click Circuits. ASYNC 2013: 183-190- [c27]Sebastiaan J. C. Joosten, Bernard van Gastel, Julien Schmaltz: A Macro for Reusing Abstract Functions and Theorems. ACL2 2013: 29-41
- [c26]Freek Verbeek, Julien Schmaltz: Verification of Building Blocks for Asynchronous Circuits. ACL2 2013: 70-84
- [c25]
- 2012
- [j9]Freek Verbeek, Julien Schmaltz: Proof Pearl: A Formal Proof of Dally and Seitz' Necessary and Sufficient Condition for Deadlock-Free Routing in Interconnection Networks. J. Autom. Reasoning 48(4): 419-439 (2012)
- [j8]Faranak Heidarian, Julien Schmaltz, Frits W. Vaandrager: Analysis of a clock synchronization protocol for wireless sensor networks. Theor. Comput. Sci. 413(1): 87-105 (2012)
- [j7]Freek Verbeek, Julien Schmaltz: Easy Formal Specification and Validation of Unbounded Networks-on-Chips Architectures. ACM Trans. Design Autom. Electr. Syst. 17(1): 1 (2012)
- [j6]Freek Verbeek, Julien Schmaltz: Towards the formal verification of cache coherency at the architectural level. ACM Trans. Design Autom. Electr. Syst. 17(3): 20 (2012)
- [c24]Abdulaziz Alhussien, Nader Bagherzadeh, Freek Verbeek, Bernard van Gastel, Julien Schmaltz: A formally verified deadlock-free routing function in a fault-tolerant NoC architecture. SBCCI 2012: 1-6
- 2011
- [j5]Freek Verbeek, Julien Schmaltz: A Comment on "A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks". IEEE Trans. Parallel Distrib. Syst. 22(10): 1775-1776 (2011)
- [j4]Freek Verbeek, Julien Schmaltz: On Necessary and Sufficient Conditions for Deadlock-Free Routing in Wormhole Networks. IEEE Trans. Parallel Distrib. Syst. 22(12): 2022-2032 (2011)
- [c23]Freek Verbeek, Julien Schmaltz: Hunting deadlocks efficiently in microarchitectural models of communication fabrics. FMCAD 2011: 223-231
- [c22]Carsten Rütz, Julien Schmaltz: An Experience Report on an Industrial Case-Study about Timed Model-Based Testing with UPPAAL-TRON. ICST Workshops 2011: 39-46
- [c21]Freek Verbeek, Julien Schmaltz: Automatic verification for deadlock in networks-on-chips with adaptive routing and wormhole switching. NOCS 2011: 25-32
- [c20]Freek Verbeek, Julien Schmaltz: A Fast and Verified Algorithm for Proving Store-and-Forward Networks Deadlock-Free. PDP 2011: 3-10
- [c19]Freek Verbeek, Julien Schmaltz: Formal verification of a deadlock detection algorithm. ACL2 2011: 103-112
- [e2]Marko C. J. D. van Eekelen, Herman Geuvers, Julien Schmaltz, Freek Wiedijk (Eds.): Interactive Theorem Proving - Second International Conference, ITP 2011, Berg en Dal, The Netherlands, August 22-25, 2011. Proceedings. Lecture Notes in Computer Science 6898, Springer 2011, ISBN 978-3-642-22862-9
- [e1]David Hardin, Julien Schmaltz (Eds.): Proceedings 10th International Workshop on the ACL2 Theorem Prover and its Applications. EPTCS 70, 2011
- [i1]Julien Schmaltz: Formal verification of a time-triggered hardware interface. CoRR abs/1103.2246 (2011)
- 2010
- [j3]Jasper Berendsen, David N. Jansen, Julien Schmaltz, Frits W. Vaandrager: The axiomatization of override and update. J. Applied Logic 8(1): 141-150 (2010)
- [c18]Freek Verbeek, Julien Schmaltz: Formal specification of networks-on-chips: deadlock and evacuation. DATE 2010: 1701-1706
- [c17]Sabrina von Styp, Henrik C. Bohnenkamp, Julien Schmaltz: A Conformance Testing Relation for Symbolic Timed Automata. FORMATS 2010: 243-255
- [c16]Fides Aarts, Julien Schmaltz, Frits W. Vaandrager: Inference and Abstraction of the Biometric Passport. ISoLA (1) 2010: 673-686
- [c15]Freek Verbeek, Julien Schmaltz: A Formal Proof of a Necessary and Sufficient Condition for Deadlock-Free Adaptive Networks. ITP 2010: 67-82
2000 – 2009
- 2009
- [j2]Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz: A Formal Approach to the Verification of Networks on Chip. EURASIP J. Emb. Sys. 2009 (2009)
- [c14]Faranak Heidarian, Julien Schmaltz, Frits W. Vaandrager: Analysis of a Clock Synchronization Protocol for Wireless Sensor Networks. FM 2009: 516-531
- [c13]Tom van den Broek, Julien Schmaltz: Towards a formally verified network-on-chip. FMCAD 2009: 184-187
- [c12]Wojciech Mostowski, Erik Poll, Julien Schmaltz, Jan Tretmans, Ronny Wichers Schreur: Model-Based Testing of Electronic Passports. FMICS 2009: 207-209
- 2008
- [j1]Julien Schmaltz, Dominique Borrione: A functional formalization of on chip communications. Formal Asp. Comput. 20(3): 241-258 (2008)
- [c11]
- [c10]Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz: Executable formal specification and validation of NoC communication infrastructures. SBCCI 2008: 176-181
- 2007
- [c9]Julien Schmaltz: A Formal Model of Clock Domain Crossing and Automated Verification of Time-Triggered Hardware. FMCAD 2007: 223-230
- [c8]Dominique Borrione, Amr Helmy, Laurence V. Pierre, Julien Schmaltz: A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study. NOCS 2007: 127-136
- 2006
- [c7]Julien Schmaltz, Dominique Borrione: Towards a formal theory of on chip communications in the ACL2 logic. ACL2 2006: 47-56
- [c6]Julien Schmaltz, Dominique Borrione: Formalizing On Chip Communications in a Functional Style. Trustworthy Software 2006
- [c5]
- 2005
- [c4]
- 2004
- [c3]Julien Schmaltz, Dominique Borrione: A Functional Approach to the Formal Specification of Networks on Chip. FMCAD 2004: 52-66
- [c2]Ghiath Al Sammane, Julien Schmaltz, Diana Toma, Pierre Ostier, Dominique Borrione: TheoSim: combining symbolic simulation and theorem proving for hardware verification. SBCCI 2004: 60-65
- 2003
- [c1]Ghiath Al Sammane, Diana Toma, Julien Schmaltz, Pierre Ostier, Dominique Borrione: Constrained Symbolic Simulation with Mathematica and ACL2. CHARME 2003: 150-157
Coauthor Index
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last updated on 2013-10-02 11:06 CEST by the dblp team