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Souradip Sarkar
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2010 – 2019
- 2019
- [c8]Souradip Sarkar, Purushotham Murugappa, Manil Dev Gomony:
A Reconfigurable Architecture for Posit Arithmetic. DSD 2019: 82-87 - 2018
- [c7]Souradip Sarkar, Manil Dev Gomony:
Quater-imaginary base for complex number arithmetic circuits. DATE 2018: 1481-1483 - [c6]Fabio Pianese, Matteo Signorini, Souradip Sarkar:
Small Transactions with Sustainable Incentives. NTMS 2018: 1-5 - 2012
- [j2]Turbo Majumder, Souradip Sarkar, Partha Pratim Pande, Ananth Kalyanaraman:
NoC-Based Hardware Accelerator for Breakpoint Phylogeny. IEEE Trans. Computers 61(6): 857-869 (2012) - [c5]Wim Heirman, Souradip Sarkar, Trevor E. Carlson, Ibrahim Hur, Lieven Eeckhout:
Power-aware multi-core simulation for early design stage hardware/software co-optimization. PACT 2012: 3-12 - 2011
- [c4]Wim Heirman, Trevor E. Carlson, Souradip Sarkar, Pieter Ghysels, Wim Vanroose, Lieven Eeckhout:
Using Fast and Accurate Simulation to Explore Hardware/Software Trade-offs in the Multi-Core Era. PARCO 2011: 343-350 - 2010
- [j1]Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pratim Pande, Ananth Kalyanaraman:
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment. IEEE Trans. Computers 59(1): 29-41 (2010) - [c3]Turbo Majumder, Souradip Sarkar, Partha Pratim Pande, Ananth Kalyanaraman:
An optimized NoC architecture for accelerating TSP kernels in breakpoint median problem. ASAP 2010: 89-96 - [c2]Souradip Sarkar, Turbo Majumder, Ananth Kalyanaraman, Partha Pratim Pande:
Hardware accelerators for biocomputing: A survey. ISCAS 2010: 3789-3792
2000 – 2009
- 2007
- [c1]Jabulani Nyathi, Souradip Sarkar, Partha Pratim Pande:
Multiple clock domain synchronization for network on chip architectures. SoCC 2007: 291-294
Coauthor Index
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