Sachin S. Sapatnekar

Sachin S. Sapatnekar: Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 32(1): 1 (2013)

Pingqiang Zhou, Vivek Mishra, Sachin S. Sapatnekar: Placement optimization of power supply pads based on locality. DATE 2013: 1655-1660

Yaoguang Wei, Zhuo Li, Cliff C. N. Sze, Shiyan Hu, Charles J. Alpert, Sachin S. Sapatnekar: CATALYST: planning layer directives for effective design closure. DATE 2013: 1873-1878

John Keane, Chris H. Kim, Qunzeng Liu, Sachin S. Sapatnekar: Process and Reliability Sensors for Nanoscale CMOS. IEEE Design & Test of Computers 29(5): 8-17 (2012)

Sachin S. Sapatnekar: Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 31(1): 1 (2012)

Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar: Optimized 3D Network-on-Chip Design Using Simulated Allocation. ACM Trans. Design Autom. Electr. Syst. 17(2): 12 (2012)

Haifeng Qian, Sachin S. Sapatnekar, Eren Kursun: Fast poisson solvers for thermal analysis. ACM Trans. Design Autom. Electr. Syst. 17(3): 32 (2012)

Jianxin Fang, Sachin S. Sapatnekar: Scalable Methods for Analyzing the Circuit Failure Probability Due to Gate Oxide Breakdown. IEEE Trans. VLSI Syst. 20(11): 1960-1973 (2012)

Saket Gupta, Sachin S. Sapatnekar: Compact Current Source Models for Timing Analysis Under Temperature and Body Bias Variations. IEEE Trans. VLSI Syst. 20(11): 2104-2117 (2012)

Baktash Boghrati, Sachin S. Sapatnekar: Incremental power network analysis using backward random walks. ASP-DAC 2012: 41-46

Saket Gupta, Sachin S. Sapatnekar: GNOMO: Greater-than-NOMinal Vdd operation for BTI mitigation. ASP-DAC 2012: 271-276

Jianxin Fang, Sachin S. Sapatnekar: The impact of hot carriers on timing in large circuits. ASP-DAC 2012: 591-596

Saket Gupta, Sachin S. Sapatnekar: BTI-aware design using variable latency units. ASP-DAC 2012: 775-780

Ayan Paul, Matt Amrein, Saket Gupta, Arvind Vinod, Abhishek Arun, Sachin S. Sapatnekar, Chris H. Kim: Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors. CICC 2012: 1-4

Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar: GLARE: global and local wiring aware routability evaluation. DAC 2012: 768-773

Jianxin Fang, Saket Gupta, Sanjay V. Kumar, Sravan K. Marella, Vivek Mishra, Pingqiang Zhou, Sachin S. Sapatnekar: Circuit reliability: From Physics to Architectures: Embedded tutorial paper. ICCAD 2012: 243-246

Pingqiang Zhou, Won Ho Choi, Bongjin Kim, Chris H. Kim, Sachin S. Sapatnekar: Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications. ICCAD 2012: 263-270

Sravan K. Marella, Sanjay V. Kumar, Sachin S. Sapatnekar: A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations. ICCAD 2012: 317-324

Jieming Yin, Pingqiang Zhou, Anup Holey, Sachin S. Sapatnekar, Antonia Zhai: Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems. ISLPED 2012: 57-62

Sachin S. Sapatnekar: Overcoming Variations in Nanometer-Scale Technologies. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(1): 5-18 (2011)

Sachin S. Sapatnekar: Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 30(1): 1 (2011)

Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits. IEEE Trans. VLSI Syst. 19(4): 603-614 (2011)

Jianxin Fang, Sachin S. Sapatnekar: Accounting for inherent circuit resilience and process variations in analyzing gate oxide reliability. ASP-DAC 2011: 689-694

Pingqiang Zhou, Dong Jiao, Chris H. Kim, Sachin S. Sapatnekar: Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network. CICC 2011: 1-4

Jaeha Kung, Inhak Han, Sachin S. Sapatnekar, Youngsoo Shin: Thermal signature: a simple yet accurate thermal index for floorplan optimization. DAC 2011: 108-113

Baktash Boghrati, Sachin S. Sapatnekar: A scaled random walk solver for fast power grid analysis. DATE 2011: 38-43

T. Kolpe, Antonia Zhai, Sachin S. Sapatnekar: Enabling improved power management in multicore processors through clustered DVFS. DATE 2011: 293-298

Sachin S. Sapatnekar: The whys and hows of thermal management. ISLPED 2011: 283-284

Pingqiang Zhou, Jieming Yin, Antonia Zhai, Sachin S. Sapatnekar: NoC frequency scaling with flexible-pipeline routers. ISLPED 2011: 403-408

Sachin S. Sapatnekar: Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 29(1): 1 (2010)

Qunzeng Liu, Sachin S. Sapatnekar: Capturing Post-Silicon Variations Using a Representative Critical Path. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 211-222 (2010)

Saket Gupta, Sachin S. Sapatnekar: Current source modeling in the presence of body bias. ASP-DAC 2010: 199-204

Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar: Application-specific 3D Network-on-Chip design using simulated allocation. ASP-DAC 2010: 517-522

Yaoguang Wei, Jiang Hu, Frank Liu, Sachin S. Sapatnekar: Physical design techniques for optimizing RTA-induced variations. ASP-DAC 2010: 745-750

Baktash Boghrati, Sachin S. Sapatnekar: Incremental solution of power grids using random walks. ASP-DAC 2010: 757-762

Haifeng Qian, Sachin S. Sapatnekar: Fast Poisson solvers for thermal analysis. ICCAD 2010: 698-702

Sachin S. Sapatnekar: Adding a new dimension to physical design. ISPD 2010: 55

Yaoguang Wei, Sachin S. Sapatnekar: Dummy fill optimization for enhanced manufacturability. ISPD 2010: 97-104

Jianxin Fang, Sachin S. Sapatnekar: Scalable methods for the analysis and optimization of gate oxide breakdown. ISQED 2010: 638-645

Sachin S. Sapatnekar (Ed.): Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010. ACM 2010, isbn 978-1-4503-0002-5

Sachin S. Sapatnekar: Technical perspective - Where the chips may fall. Commun. ACM 52(8): 94 (2009)

Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar: Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity. IEEE Design & Test of Computers 26(5): 15-25 (2009)

Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan: Fast and Accurate Statistical Criticality Computation Under Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 350-363 (2009)

Qunzeng Liu, Sachin S. Sapatnekar: A Framework for Scalable Postsilicon Statistical Delay Prediction Under Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 28(8): 1201-1212 (2009)

Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang: A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips. IEEE Trans. on CAD of Integrated Circuits and Systems 28(9): 1295-1306 (2009)

Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar: Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors. ASP-DAC 2009: 179-184

Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: Adaptive techniques for overcoming performance degradation due to aging in digital circuits. ASP-DAC 2009: 284-289

Sachin S. Sapatnekar: Addressing thermal and power delivery bottlenecks in 3D circuits. ASP-DAC 2009: 423-428

Qunzeng Liu, Sachin S. Sapatnekar: Synthesizing a representative critical path for post-silicon delay prediction. ISPD 2009: 183-190

Sachin S. Sapatnekar: Building your yield of dreams. IEEE Design & Test of Computers 25(2): 194-195 (2008)

Sachin S. Sapatnekar: Adapting to the times [review of Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice (Wang, A. and Naffziger, S., Eds.; 2008)]. IEEE Design & Test of Computers 25(5): 496-497 (2008)

Yong Zhan, Sanjay V. Kumar, Sachin S. Sapatnekar: Thermally Aware Design. Foundations and Trends in Electronic Design Automation 2(3): 255-370 (2008)

Tianpei Zhang, Sachin S. Sapatnekar: Buffering global interconnects in structured ASIC design. Integration 41(2): 171-182 (2008)

Yong Zhan, Sachin S. Sapatnekar: Automated module assignment in stacked-Vdd designs for high-efficiency power delivery. JETC 4(4) (2008)

Haifeng Qian, Sachin S. Sapatnekar: Stochastic Preconditioning for Diagonally Dominant Matrices. SIAM J. Scientific Computing 30(3): 1178-1204 (2008)

Shrirang K. Karandikar, Sachin S. Sapatnekar: Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 45-58 (2008)

Jaskirat Singh, Sachin S. Sapatnekar: A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 160-173 (2008)

Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar: A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 295-308 (2008)

Jie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim: Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property. IEEE Trans. VLSI Syst. 16(2): 206-209 (2008)

Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: Body Bias Voltage Computations for Process and Temperature Compensation. IEEE Trans. VLSI Syst. 16(3): 249-262 (2008)

John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim: Stack Sizing for Optimal Current Drivability in Subthreshold Circuits. IEEE Trans. VLSI Syst. 16(5): 598-602 (2008)

Sachin S. Sapatnekar, Eshel Haritan, Kurt Keutzer, Anirudh Devgan, Desmond Kirkpatrick, Stephen Meier, Duaine Pryor, Tom Spyrou: Reinventing EDA with manycore processors. DAC 2008: 126-127

Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang: A progressive-ILP based routing algorithm for cross-referencing biochips. DAC 2008: 284-289

Sanjay V. Kumar, Chandramouli V. Kashyap, Sachin S. Sapatnekar: A framework for block-based timing sensitivity analysis. DAC 2008: 688-693

Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar: Routing Congestion in VLSI Circuits - Estimation and Optimization. Series on integrated circuits and systems, Springer 2007, isbn 978-0-387-30037-5, pp. I-XIV, 1-248

Sachin S. Sapatnekar: Book Review: An Assay of Biochips. IEEE Design & Test of Computers 24(4): 402-403 (2007)

Sachin S. Sapatnekar, Leon Stok: DAC Highlights. IEEE Design & Test of Computers 24(5): 502-504 (2007)

Krishnendu Chakrabarty, Sachin S. Sapatnekar: Editorial to special issue DAC 2006. JETC 3(3) (2007)

Gustavo de Veciana, Marcello Lajolo, Chen He, Enrico Macii, Sachin S. Sapatnekar: In Memoriam: Margarida F. Jacome. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1549-1550 (2007)

Yong Zhan, Sachin S. Sapatnekar: High-Efficiency Green Function-Based Thermal Simulation Algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1661-1675 (2007)

Hongliang Chang, Sachin S. Sapatnekar: Prediction of leakage power under process uncertainties. ACM Trans. Design Autom. Electr. Syst. 12(2) (2007)

Tianpei Zhang, Sachin S. Sapatnekar: Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. IEEE Trans. VLSI Syst. 15(6): 624-636 (2007)

Jie Gu, Sachin S. Sapatnekar, Chris H. Kim: Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift. DAC 2007: 87-92

Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: NBTI-Aware Synthesis of Digital Circuits. DAC 2007: 370-375

Qunzeng Liu, Sachin S. Sapatnekar: Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations. DAC 2007: 497-502

Brent Goplen, Sachin S. Sapatnekar: Placement of 3D ICs with Thermal and Interlayer Via Considerations. DAC 2007: 626-631

Felipe S. Marques, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis: DAG based library-free technology mapping. ACM Great Lakes Symposium on VLSI 2007: 293-298

Sachin S. Sapatnekar: Computer-aided design of 3d integrated circuits. ACM Great Lakes Symposium on VLSI 2007: 317

Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan: Clustering based pruning for statistical criticality computation under process variations. ICCAD 2007: 340-343

Dmitry Bufistov, Jordi Cortadella, Michael Kishinevsky, Sachin S. Sapatnekar: A general model for performance optimization of sequential systems. ICCAD 2007: 362-369

Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar: Module assignment for pin-limited designs under the stacked-Vdd paradigm. ICCAD 2007: 656-659

Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi: Probabilistic Congestion Prediction with Partial Blockages. ISQED 2007: 841-846

Sachin S. Sapatnekar, Grant Martin: DAC Highlights. IEEE Design & Test of Computers 23(3): 182-184 (2006)

Sachin S. Sapatnekar: Book Reviews: Plumbing the Depths of Leakage. IEEE Design & Test of Computers 23(4): 318-319 (2006)

Rupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar: Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 625-636 (2006)

Jaskirat Singh, Sachin S. Sapatnekar: Partition-Based Algorithm for Power Grid Design Using Locality. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 664-677 (2006)

Brent Goplen, Sachin S. Sapatnekar: Placement of Thermal Vias in 3-D ICs Using Various Thermal Objectives. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 692-709 (2006)

Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze: Accurate estimation of global buffer delay within a floorplan. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1140-1145 (2006)

Yong Zhan, Brent Goplen, Sachin S. Sapatnekar: Electrothermal analysis and optimization techniques for nanoscale integrated circuits. ASP-DAC 2006: 219-222

Tianpei Zhang, Yong Zhan, Sachin S. Sapatnekar: Temperature-aware routing in 3D ICs. ASP-DAC 2006: 309-314

Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems. ASP-DAC 2006: 559-564

Yong Zhan, Yan Feng, Sachin S. Sapatnekar: A fixed-die floorplanning algorithm using an analytical approach. ASP-DAC 2006: 771-776

Jaskirat Singh, Sachin S. Sapatnekar: Statistical timing analysis with correlated non-gaussian parameters using independent component analysis. DAC 2006: 155-160

John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim: Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing. DAC 2006: 425-428

Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: An analytical model for negative bias temperature instability. ICCAD 2006: 493-496

Vidyasagar Nookala, David J. Lilja, Sachin S. Sapatnekar: Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis. ISLPED 2006: 298-303

Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar: Comparing simulation techniques for microarchitecture-aware floorplanning. ISPASS 2006: 80-88

Keith A. Bowman, Michael Orshansky, Sachin S. Sapatnekar: Tutorial II: Variability and Its Impact on Design. ISQED 2006: 5

Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: Impact of NBTI on SRAM Read Stability and Design for Reliability. ISQED 2006: 210-218

Leomar S. da Rosa Jr., Felipe S. Marques, Tiago Muller Gil Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis: Fast disjoint transistor networks from BDDs. SBCCI 2006: 137-142

Sachin S. Sapatnekar: An EDA compendium. IEEE Design & Test of Computers 22(1): 74-75 (2005)

Sachin S. Sapatnekar: Empowering the designer. IEEE Design & Test of Computers 22(3): 280-281 (2005)

Sachin S. Sapatnekar, Kevin J. Nowka: Guest Editors' Introduction: New Dimensions in 3D Integration. IEEE Design & Test of Computers 22(6): 496-497 (2005)

Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar: Placement and Routing in 3D Integrated Circuits. IEEE Design & Test of Computers 22(6): 520-531 (2005)

Sachin S. Sapatnekar: Designing "Vary" Good Circuitry. IEEE Design & Test of Computers 22(6): 596-597 (2005)

Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar: Early-stage power grid analysis for uncertain working modes. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 676-682 (2005)

Jaskirat Singh, Sachin S. Sapatnekar: Congestion-aware topology optimization of structured power/ground networks. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 683-695 (2005)

Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang: A predictive distributed congestion metric with application to technology mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 696-710 (2005)

Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar: Power grid analysis using random walks. IEEE Trans. on CAD of Integrated Circuits and Systems 24(8): 1204-1224 (2005)

Hongliang Chang, Sachin S. Sapatnekar: Statistical timing analysis under spatial correlations. IEEE Trans. on CAD of Integrated Circuits and Systems 24(9): 1467-1482 (2005)

Rupesh S. Shelar, Sachin S. Sapatnekar: BDD decomposition for delay oriented pass transistor logic synthesis. IEEE Trans. VLSI Syst. 13(8): 957-970 (2005)

Shrirang K. Karandikar, Sachin S. Sapatnekar: Fast comparisons of circuit implementations. IEEE Trans. VLSI Syst. 13(12): 1329-1339 (2005)

Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar: Gate oxide leakage and delay tradeoffs for dual-T/sub ox/ circuits. IEEE Trans. VLSI Syst. 13(12): 1362-1375 (2005)

Tianpei Zhang, Sachin S. Sapatnekar: Buffering global interconnects in structured ASIC design. ASP-DAC 2005: 23-26

Yong Zhan, Sachin S. Sapatnekar: Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up. ASP-DAC 2005: 87-92

Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, Sachin S. Sapatnekar: Robust gate sizing by geometric programming. DAC 2005: 315-320

Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar: Net weighting to reduce repeater counts during placement. DAC 2005: 503-508

Hongliang Chang, Sachin S. Sapatnekar: Full-chip analysis of leakage power under process variations, including spatial correlations. DAC 2005: 523-528

Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar: Microarchitecture-aware floorplanning using a statistical design of experiments approach. DAC 2005: 579-584

Felipe S. Marques, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis: A new approach to the use of satisfiability in false path detection. ACM Great Lakes Symposium on VLSI 2005: 308-311

Yong Zhan, Sachin S. Sapatnekar: A high efficiency full-chip thermal simulation algorithm. ICCAD 2005: 635-638

Haifeng Qian, Sachin S. Sapatnekar: A hybrid linear equation solver and its application in quadratic placement. ICCAD 2005: 905-909

Felipe Ribeiro Schneider, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis: Exact lower bound for the number of switches in series to implement a combinational logic cell. ICCD 2005: 357-362

Vidyasagar Nookala, Sachin S. Sapatnekar: Designing optimized pipelined global interconnects: algorithms and methodology impact. ISCAS (1) 2005: 608-611

Shrirang K. Karandikar, Sachin S. Sapatnekar: Fast estimation of area-delay trade-offs in circuit sizing. ISCAS (4) 2005: 3575-3578

Jaskirat Singh, Sachin S. Sapatnekar: A fast algorithm for power grid design. ISPD 2005: 70-77

Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar: An efficient technology mapping algorithm targeting routing congestion under delay constraints. ISPD 2005: 137-144

Brent Goplen, Sachin S. Sapatnekar: Thermal via placement in 3D ICs. ISPD 2005: 167-174

Sachin S. Sapatnekar, Jaijeet S. Roychowdhury, Ramesh Harjani: High-Speed Interconnect Technology: On-Chip and Off-Chip. VLSI Design 2005: 7-

Sachin S. Sapatnekar: Timing. Kluwer 2004, isbn 978-1-4020-7671-8, pp. I-IX, 1-294

Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif: A methodology for the simultaneous design of supply and signal networks. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1614-1624 (2004)

Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi: A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints. ACM Trans. Design Autom. Electr. Syst. 9(3): 273-289 (2004)

Haifeng Qian, Sachin S. Sapatnekar: Hierarchical random-walk algorithms for power grid analysis. ASP-DAC 2004: 499-504

Vidyasagar Nookala, Sachin S. Sapatnekar: A method for correcting the functionality of a wire-pipelined circuit. DAC 2004: 570-575

Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar: Tradeoffs between date oxide leakage and delay for dual T_ox circuits. DAC 2004: 761-766

Yong Zhan, Sachin S. Sapatnekar: Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming. DATE 2004: 622-629

Shrirang K. Karandikar, Sachin S. Sapatnekar: Fast Comparisons of Circuit Implementations. DATE 2004: 910-915

Haifeng Qian, Joseph N. Kozhaya, Sani R. Nassif, Sachin S. Sapatnekar: A chip-level electrostatic discharge simulation strategy. ICCAD 2004: 315-318

Shrirang K. Karandikar, Sachin S. Sapatnekar: Logical effort based technology mapping. ICCAD 2004: 419-422

Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze: Accurate estimation of global buffer delay within a floorplan. ICCAD 2004: 706-711

Tianpei Zhang, Sachin S. Sapatnekar: Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. ICCD 2004: 93-98

Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar: Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits. ICCD 2004: 228-233

Jaskirat Singh, Sachin S. Sapatnekar: Topology optimization of structured power/ground networks. ISPD 2004: 116-123

Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar: Early-stage power grid analysis for uncertain working modes. ISPD 2004: 132-137

Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang: A predictive distributed congestion metric and its application to technology mapping. ISPD 2004: 210-217

Hongliang Chang, Haifeng Qian, Sachin S. Sapatnekar: The Certainty of Uncertainty: Randomness in Nanometer Design. PATMOS 2004: 36-47

Sachin S. Sapatnekar: High-Performance Power Grids For Nanometer Technologies. VLSI Design 2004: 839-844

Sachin S. Sapatnekar, Haihua Su: Analysis and Optimization of Power Grids. IEEE Design & Test of Computers 20(3): 7-15 (2003)

Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: Fast on-chip inductance simulation using a precorrected-FFT method. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 49-66 (2003)

Charles J. Alpert, Sachin S. Sapatnekar: Guest editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 385-386 (2003)

Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif: Optimal decoupling capacitor sizing and placement for standard-cell layout designs. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 428-436 (2003)

Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia: A practical methodology for early buffer and wire resource allocation. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 573-583 (2003)

Haihua Su, Kaushik Gala, Sachin S. Sapatnekar: Analysis and optimization of structured power/ground networks. IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1533-1544 (2003)

Shrirang K. Karandikar, Sachin S. Sapatnekar: Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect. IEEE Trans. VLSI Syst. 11(6): 1094-1105 (2003)

Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar: Random walks in a supply network. DAC 2003: 93-98

Brent Goplen, Sachin S. Sapatnekar: Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach. ICCAD 2003: 86-90

Hongliang Chang, Sachin S. Sapatnekar: Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal. ICCAD 2003: 621-626

Venkatesan Rajappan, Sachin S. Sapatnekar: An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk. ICCD 2003: 76-

Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: Table look-up based compact modeling for on-chip interconnect timing and noise analysis. ISCAS (4) 2003: 668-671

Guoqiang Chen, Sachin S. Sapatnekar: Partition-driven standard cell thermal placement. ISPD 2003: 75-80

Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert: Probability-driven routing in a datapath environment. Integration 31(2): 159-182 (2002)

Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw: Hierarchical analysis of power distribution networks. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 159-168 (2002)

Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi: Fast and exact transistor sizing based on iterative relaxation. IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 568-581 (2002)

Jiang Hu, Sachin S. Sapatnekar: A timing-constrained simultaneous global routing algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1025-1036 (2002)

Min Zhao, Sachin S. Sapatnekar: Technology mapping algorithms for domino logic. ACM Trans. Design Autom. Electr. Syst. 7(2): 306-335 (2002)

Jatuchai Pangjun, Sachin S. Sapatnekar: Low-power clock distribution using multiple voltages and reduced swings. IEEE Trans. VLSI Syst. 10(3): 309-318 (2002)

Haitian Hu, Sachin S. Sapatnekar: Efficient inductance extraction using circuit-aware techniques. IEEE Trans. VLSI Syst. 10(6): 746-761 (2002)

Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif: Congestion-driven codesign of power and signal networks. DAC 2002: 64-69

Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: A precorrected-FFT method for simulating on-chip inductance. ICCAD 2002: 221-227

Mahesh Ketkar, Sachin S. Sapatnekar: Standby power optimization via transistor sizing and dual threshold voltage assignment. ICCAD 2002: 375-378

Haitian Hu, Sachin S. Sapatnekar: Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques. ICCD 2002: 434-

Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif: An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts. ISPD 2002: 68-73

Rupesh S. Shelar, Sachin S. Sapatnekar: Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits. IWLS 2002: 209-214

Tianpei Zhang, Sachin S. Sapatnekar: Optimized pin assignment for lower routing congestion after floorplanning phase. SLIP 2002: 17-21

Rupesh S. Shelar, Sachin S. Sapatnekar: An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. VLSI Design 2002: 87-92

Jiang Hu, Sachin S. Sapatnekar: A survey on multi-net global routing for integrated circuits. Integration 31(1): 1-49 (2001)

Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar: Steiner tree optimization for buffers, blockages, and bays. IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 556-562 (2001)

Martin Kuhlmann, Sachin S. Sapatnekar: Exact and efficient crosstalk estimation. IEEE Trans. on CAD of Integrated Circuits and Systems 20(7): 858-866 (2001)

Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji: Technology mapping for high-performance static CMOS and pass transistor logic designs. IEEE Trans. VLSI Syst. 9(5): 577-589 (2001)

Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia: A Practical Methodology for Early Buffer and Wire Resource Allocation. DAC 2001: 189-194

Min Zhao, Sachin S. Sapatnekar: A New Structural Pattern Matching Algorithm for Technology Mapping. DAC 2001: 371-376

Shrirang K. Karandikar, Sachin S. Sapatnekar: Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect. DAC 2001: 377-382

Haihua Su, Sachin S. Sapatnekar: Hybrid Structured Clock Network Construction. ICCAD 2001: 333-336

Rupesh S. Shelar, Sachin S. Sapatnekar: Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits. ICCAD 2001: 449-452

Jiang Hu, Sachin S. Sapatnekar: Performance Driven Global Routing Through Gradual Refinement. ICCD 2001: 481-483

Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar: Steiner tree optimization for buffers. Blockages and bays. ISCAS (5) 2001: 399-402

Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia: Buffered Steiner trees for difficult instances. ISPD 2001: 4-9

Noel Menezes, Sachin S. Sapatnekar: Optimization and Analysis Techniques for the Deep Submicron Regime. VLSI Design 2001: 3-4

Jiang Hu, Sachin S. Sapatnekar: Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model. IEEE Trans. on CAD of Integrated Circuits and Systems 19(4): 446-458 (2000)

Sachin S. Sapatnekar: A timing model incorporating the effect of crosstalk on delay andits application to optimal channel routing. IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 550-559 (2000)

Kishore Kasamsetty, Mahesh Ketkar, Sachin S. Sapatnekar: A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem [CMOS gates]. IEEE Trans. on CAD of Integrated Circuits and Systems 19(7): 779-788 (2000)

Min Zhao, Sachin S. Sapatnekar: Timing-driven partitioning and timing optimization of mixedstatic-domino implementations. IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1322-1336 (2000)

Sachin S. Sapatnekar, Weitong Chuang: Power-delay optimizations in gate sizing. ACM Trans. Design Autom. Electr. Syst. 5(1): 98-114 (2000)

Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David Blaauw: Hierarchical analysis of power distribution networks. DAC 2000: 150-155

Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi: MINFLOTRANSIT: min-cost flow based transistor sizing tool. DAC 2000: 649-664

Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapatnekar: Convex delay models for transistor sizing. DAC 2000: 655-660

Jiang Hu, Sachin S. Sapatnekar: A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets. ICCAD 2000: 99-103

Haihua Su, Kaushik Gala, Sachin S. Sapatnekar: Fast Analysis and Optimization of Power/Ground Networks. ICCAD 2000: 477-480

Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert: Datapath routing based on a decongestion metric. ISPD 2000: 122-127

Sachin S. Sapatnekar: Capturing the Effect of Crosstalk on Delay. VLSI Design 2000: 364-369

Naresh Maheshwari, Sachin S. Sapatnekar: Retiming control logic. Integration 28(1): 33-53 (1999)

Huibo Hou, Jiang Hu, Sachin S. Sapatnekar: Non-Hanan routing. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 436-444 (1999)

Naresh Maheshwari, Sachin S. Sapatnekar: Optimizing large multiphase level-clocked circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1249-1264 (1999)

Jiang Hu, Sachin S. Sapatnekar: FAR-DS: Full-Plane AWE Routing with Driver Sizing. DAC 1999: 84-89

Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi: Marsh: min-area retiming with setup and hold constraints. ICCAD 1999: 2-6

Yanbin Jiang, Sachin S. Sapatnekar: An integrated algorithm for combined placement and libraryless technology mapping. ICCAD 1999: 102-106

Min Zhao, Sachin S. Sapatnekar: Timing-driven partitioning for two-phase domino and mixed static/domino implementations. ICCAD 1999: 107-110

Martin Kuhlmann, Sachin S. Sapatnekar, Keshab K. Parhi: Efficient Crosstalk Estimation. ICCD 1999: 266-

Jatuchai Pangjun, Sachin S. Sapatnekar: Clock distribution using multiple voltages. ISLPED 1999: 145-150

Jiang Hu, Sachin S. Sapatnekar: Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model. ISPD 1999: 133-138

Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn: Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 17(2): 173-182 (1998)

Naresh Maheshwari, Sachin S. Sapatnekar: Efficient retiming of large circuits. IEEE Trans. VLSI Syst. 6(1): 74-83 (1998)

Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim: Interleaving buffer insertion and transistor sizing into a single optimization. IEEE Trans. VLSI Syst. 6(4): 625-633 (1998)

Naresh Maheshwari, Sachin S. Sapatnekar: Efficient Minarea Retiming of Large Level-Clocked Circuits. DATE 1998: 840-845

Min Zhao, Sachin S. Sapatnekar: Technology mapping for domino logic. ICCAD 1998: 248-251

Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji: A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic. ICCD 1998: 276-281

Huibo Hou, Sachin S. Sapatnekar: Routing tree topology construction to meet interconnect timing constraints. ISPD 1998: 205-210

Shankar Ramaswamy, Sachin S. Sapatnekar, Prithviraj Banerjee: A Framework for Exploiting Task and Data Parallelism on Distributed Memory Multicomputers. IEEE Trans. Parallel Distrib. Syst. 8(11): 1098-1116 (1997)

Naresh Maheshwari, Sachin S. Sapatnekar: An Improved Algorithm for Minimum-Area Retiming. DAC 1997: 2-7

Naresh Maheshwari, Sachin S. Sapatnekar: Minimum area retiming with equivalent initial states. ICCAD 1997: 216-219

Juho Kim, Cyrus Bamji, Yanbin Jiang, Sachin S. Sapatnekar: Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs. ISPD 1997: 130-135

Sachin S. Sapatnekar: Wire sizing as a convex optimization problem: exploring the area-delay tradeoff. IEEE Trans. on CAD of Integrated Circuits and Systems 15(8): 1001-1011 (1996)

Piyush K. Sancheti, Sachin S. Sapatnekar: Optimal design of macrocells for low power and high speed. IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1160-1166 (1996)

Sachin S. Sapatnekar, Rahul B. Deokar: Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1237-1248 (1996)

Daksh Lehther, Sachin S. Sapatnekar: Clock tree synthesis for multi-chip modules. ICCAD 1996: 50-53

Naresh Maheshwari, Sachin S. Sapatnekar: A Practical Algorithm for Retiming Level-Clocked Circuits. ICCD 1996: 440-

Jatan C. Shah, Sachin S. Sapatnekar: Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs. VLSI Design 1996: 346-351

Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj: Timing and area optimization for standard-cell VLSI circuit design. IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 308-320 (1995)

Rahul B. Deokar, Sachin S. Sapatnekar: A Fresh Look at Retiming Via Clock Skew Optimization. DAC 1995: 310-315

Sachin S. Sapatnekar, Weitong Chuang: Power vs. delay in gate sizing: conflicting objectives? ICCAD 1995: 463-466

Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn: Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. ICCAD 1995: 467-470

Piyush K. Sancheti, Sachin S. Sapatnekar: Layout Optimization Using Arbitrarily High Degree Posynomial Models. ISCAS 1995: 53-56

Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang: Convexity-based algorithms for design centering. IEEE Trans. on CAD of Integrated Circuits and Systems 13(12): 1536-1549 (1994)

Sachin S. Sapatnekar: RC Interconnect Optimization Under the Elmore Delay Model. DAC 1994: 387-391

Shankar Ramaswamy, Sachin S. Sapatnekar, Prithviraj Banerjee: A Convex Programming Approach for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers. ICPP 1994: 116-125

Jaewon Kim, Sung-Mo Kang, Sachin S. Sapatnekar: High Performance CMOS Macromodule Layout Synthesis. ISCAS 1994: 179-182

Rahul B. Deokar, Sachin S. Sapatnekar: A Graph-Theoretic Approach to Clock Skew Optimization. ISCAS 1994: 407-410

Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang: An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 12(11): 1621-1634 (1993)

Sachin S. Sapatnekar, Pravin M. Vaidya, Steve M. Kang: Convexity-based algorithms for design centering. ICCAD 1993: 206-209

Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj: A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area. ICCAD 1993: 220-223

Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang: Feasible Region Approximation Using Convex Polytopes. ISCAS 1993: 1786-1789

Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya: A Convex Optimization Approach to Transistor Sizing for CMOS Circuits. ICCAD 1991: 482-485