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Maya H. Safieddine

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2010 – 2019

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2019
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Maya H. Safieddine, Fadi A. Zaraket, Rouwaida Kanj, Ali S. Elzein, Wolfgang Roesner:
Verification at RTL Using Separation of Design Concerns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(8): 1529-1542 (2019)
2016
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Maya H. Safieddine, Fadi A. Zaraket, Mohamad Jaber, Rouwaida Kanj, Mazen A. R. Saghir:
Automated FPGA implementations of BIP designs. SIES 2016: 165-170
2015
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Maya H. Safieddine, Rouwaida Kanj, Fadi A. Zaraket, Ali S. Elzein, Mohamad Jaber:
Separation of concerns for hardware components of embedded systems in BIP. ISQED 2015: 337-344

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