Juan J. Rodríguez-Andina

Juan J. Rodríguez-Andina, Luís Gomes: Guest Editorial Special Section on Information Technologies Within Engineering Education. IEEE Trans. Industrial Informatics 9(1): 546 (2013)

Judit Freijedo, Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira: Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits. J. Electronic Testing 28(4): 421-434 (2012)

Judit Freijedo, María Dolores Valdés, Lucía Costas, María José Moure, Juan J. Rodríguez-Andina, Jorge Semião, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira: Lower V_DD Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing. J. Low Power Electronics 7(2): 185-198 (2011)

Vasco Bexiga, Carlos Leong, Jorge Semião, Isabel C. Teixeira, João Paulo Teixeira, María Dolores Valdés, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas: Performance Failure Prediction Using Built-In Delay Sensors in FPGAs. FPL 2011: 301-304

Judit Freijedo, Lucía Costas, Jorge Semião, Juan J. Rodríguez-Andina, María José Moure, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira: Impact of Power Supply Voltage Variations on FPGA-Based Digital Systems Performance. J. Low Power Electronics 6(2): 339-349 (2010)

Juan J. Rodríguez-Andina, Luís Gomes, Seta Bogosyan: Current Trends in Industrial Electronics Education. IEEE Transactions on Industrial Electronics 57(10): 3245-3252 (2010)

Raul Chipana, Leticia Maria Veiras Bolzani, Fabian Vargas, Jorge Semião, Juan J. Rodríguez-Andina, Isabel C. Teixeira, Paulo J. Teixeira: Investigating the Use of BICS to detect resistive-open defects in SRAMs. IOLTS 2010: 200-201

Lucia Costas-Perez, Juan J. Rodríguez-Andina: Algorithmic Concurrent Error Detection in Complex Digital-Processing Systems. IEEE Design & Test of Computers 26(1): 60-67 (2009)

Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies. IOLTS 2009: 223-228

Jorge Semião, Marcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina, Leonardo Bisch Piccoli, Fabian Vargas, Marcelino Bicho Dos Santos, Isabel Maria Cacho Teixeira, João Paulo Teixeira: Signal Integrity Enhancement in Digital Circuits. IEEE Design & Test of Computers 25(5): 452-461 (2008)

Judit Freijedo, Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Isabel C. Teixeira, Paulo J. Teixeira: Delay Modeling for Power Noise and Temperature-Aware Design and Test of Digital Systems. J. Low Power Electronics 4(3): 385-391 (2008)

Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, Paulo J. Teixeira: Time Management for Low-Power Design of Digital Systems. J. Low Power Electronics 4(3): 410-419 (2008)

Lucia Costas-Perez, David Lago, José Fariña, Juan J. Rodríguez-Andina: Optimization of an Industrial Sensor and Data Acquisition Laboratory Through Time Sharing and Remote Access. IEEE Transactions on Industrial Electronics 55(6): 2397-2404 (2008)

J. Luis Mato, Miguel Pereira, Juan J. Rodríguez-Andina, José Fariña, Enrique Soto, Raúl Pérez: Distortion Mitigation in RF Power Amplifiers Through FPGA-Based Amplitude and Phase Predistortion. IEEE Transactions on Industrial Electronics 55(11): 4085-4093 (2008)

Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits. DDECS 2008: 34-37

Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits. IOLTS 2008: 227-232

Juan J. Rodríguez-Andina, María José Moure, María Dolores Valdés: Features, Design Tools, and Application Domains of FPGAs. IEEE Transactions on Industrial Electronics 54(4): 1810-1823 (2007)

Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits. DDECS 2007: 295-300

Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino Bicho Dos Santos, Isabel C. Teixeira, João Paulo Teixeira: Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations. DFT 2007: 303-311

Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits. IOLTS 2007: 167-172

Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Enhancing the Tolerance to Power-Supply Instability in Digital Circuits. ISVLSI 2007: 207-212

Enrique Soto, Elena Lago, Juan J. Rodríguez-Andina: FPGA Implementation of High-Performance PHM / DPHM Schedulers. FPL 2006: 1-4

Marcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Jorge Semião, Isabel C. Teixeira, João Paulo Teixeira: Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes. IOLTS 2006: 257-262

Lucía Costas, Juan J. Rodríguez-Andina: Characterization of Wavelet-Based Image Coding Systems for Algorithmic Fault Detection. DSD 2005: 64-71

Miguel Pereira, Enrique Soto, Juan J. Rodríguez-Andina, Francisco J. González-Castaño: High-Level Modelling and Detection of the Faulty Behaviour of VOQ Switches under Balanced Traffic. DSD 2005: 282-288

Marcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test. IOLTS 2005: 281-286

Santiago Fernández-Gomez, Juan J. Rodríguez-Andina, Enrique Mandado: Concurrent error detection in block ciphers. ITC 2000: 979-984

Juan J. Rodríguez-Andina, J. Alvarez, Enrique Mandado: Design of Safety Systems Using Field Programmable Gate Arrays. FPL 1994: 341-343