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Sudhakar M. Reddy
2010 – today
- 2012
[j188]Irith Pomeranz, Sudhakar M. Reddy: Reset and partial-reset-based functional broadside tests. IET Computers & Digital Techniques 6(4): 232-239 (2012)- [j187]Irith Pomeranz, Sudhakar M. Reddy: Resolution of Diagnosis Based on Transition Faults. IEEE Trans. VLSI Syst. 20(1): 172-176 (2012)
- [c364]Xiaoxin Fan, Manish Sharma, Wu-Tung Cheng, Sudhakar M. Reddy: Diagnosis of Cell Internal Defects with Multi-cycle Test Patterns. Asian Test Symposium 2012: 7-12
- [c363]Xiaoqing Wen, Sudhakar M. Reddy: Session Summary III: Power-Aware Testing: Present and Future. Asian Test Symposium 2012: 220
- [c362]Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker: TSV and DFT cost aware circuit partitioning for 3D-SOCs. ISQED 2012: 21-26
- [c361]Xiaoxin Fan, Huaxing Tang, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Brady Benware: Improved volume diagnosis throughput using dynamic design partitioning. ITC 2012: 1-10
- [c360]Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker: Functional test of small-delay faults using SAT and Craig interpolation. ITC 2012: 1-8
- [c359]Matthias Sauer, Stefan Kupferschmid, Alejandro Czutro, Sudhakar M. Reddy, Bernd Becker: Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation. VLSI Design 2012: 382-387
- 2011
- [j186]Irith Pomeranz, Sudhakar M. Reddy: Primary input cones based on test sequences in synchronous sequential circuits. IET Computers & Digital Techniques 5(1): 16-24 (2011)
- [j185]Irith Pomeranz, Sudhakar M. Reddy: Two-dimensional partially functional broadside tests. IET Computers & Digital Techniques 5(4): 247-253 (2011)
- [j184]Irith Pomeranz, Sudhakar M. Reddy: Sizes of test sets for path delay faults using strong and weak non-robust tests. IET Computers & Digital Techniques 5(5): 405-414 (2011)
- [j183]Irith Pomeranz, Sudhakar M. Reddy: Ranking of input cubes based on their lingering synchronisation effects and their use in random sequential test generation. IET Computers & Digital Techniques 5(5): 415-423 (2011)
- [j182]Irith Pomeranz, Sudhakar M. Reddy: Transparent-Segmented-Scan without the Routing Overhead of Segmented-Scan. J. Low Power Electronics 7(2): 245-253 (2011)
- [j181]Ilia Polian, John P. Hayes, Sudhakar M. Reddy, Bernd Becker: Modeling and Mitigating Transient Errors in Logic Circuits. IEEE Trans. Dependable Sec. Comput. 8(4): 537-547 (2011)
- [j180]Irith Pomeranz, Sudhakar M. Reddy: Reducing the switching activity of test sequences under transparent-scan. ACM Trans. Design Autom. Electr. Syst. 16(2): 17 (2011)
- [j179]Irith Pomeranz, Sudhakar M. Reddy: Fixed-State Tests for Delay Faults in Scan Designs. IEEE Trans. VLSI Syst. 19(1): 142-146 (2011)
- [j178]Irith Pomeranz, Sudhakar M. Reddy: Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits. IEEE Trans. VLSI Syst. 19(2): 333-337 (2011)
- [j177]Irith Pomeranz, Sudhakar M. Reddy: On Functional Broadside Tests With Functional Propagation Conditions. IEEE Trans. VLSI Syst. 19(6): 1094-1098 (2011)
- [j176]Irith Pomeranz, Sudhakar M. Reddy: Broadside and Functional Broadside Tests for Partial-Scan Circuits. IEEE Trans. VLSI Syst. 19(6): 1104-1108 (2011)
- [j175]Irith Pomeranz, Sudhakar M. Reddy: Static Test Data Volume Reduction Using Complementation or Modulo- M Addition. IEEE Trans. VLSI Syst. 19(6): 1108-1112 (2011)
- [j174]Irith Pomeranz, Sudhakar M. Reddy: Reducing the Storage Requirements of a Test Sequence by Using One or Two Background Vectors. IEEE Trans. VLSI Syst. 19(10): 1755-1764 (2011)
- [j173]Irith Pomeranz, Sudhakar M. Reddy: Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits. IEEE Trans. VLSI Syst. 19(10): 1907-1911 (2011)
- [c358]J. M. Howard, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker: Fault diagnosis aware ATE assisted test response compaction. ASP-DAC 2011: 812-817
- [c357]Xiaoxin Fan, Huaxing Tang, Sudhakar M. Reddy, Wu-Tung Cheng, Brady Benware: On Using Design Partitioning to Reduce Diagnosis Memory Footprint. Asian Test Symposium 2011: 219-225
- [c356]Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Jakub Janicki: Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating. Asian Test Symposium 2011: 267-272
- [c355]Shida Zhong, S. Saqib Khursheed, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Krishnendu Chakrabarty: Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation. Asian Test Symposium 2011: 389-394
- [c354]Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker: Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing. DATE 2011: 1424-1429
- [c353]Xiaoxin Fan, Sudhakar M. Reddy, Irith Pomeranz: Max-Fill: A method to generate high quality delay tests. DDECS 2011: 375-380
- [c352]Xun Tang, Wu-Tung Cheng, Ruifeng Guo, Huaxing Tang, Sudhakar M. Reddy: Diagnosis of Multiple Faults Based on Fault-Tuple Equivalence Tree. DFT 2011: 217-225
- [c351]Janusz Rajski, Elham K. Moghaddam, Sudhakar M. Reddy: Low power compression utilizing clock-gating. ITC 2011: 1-8
- 2010
- [j172]Irith Pomeranz, Sudhakar M. Reddy: Diagnosis of path delay faults based on low-coverage tests. IET Computers & Digital Techniques 4(2): 89-103 (2010)
- [j171]Irith Pomeranz, Sudhakar M. Reddy: Static test compaction for diagnostic test sets of full-scan circuits. IET Computers & Digital Techniques 4(5): 365-373 (2010)
- [j170]Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. International Journal of Parallel Programming 38(3-4): 185-202 (2010)
- [j169]Irith Pomeranz, Sudhakar M. Reddy: Test Sequences with Reduced and Increased Switching Activity. J. Low Power Electronics 6(2): 350-358 (2010)
- [j168]Irith Pomeranz, Sudhakar M. Reddy: Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis. IEEE Trans. Computers 59(2): 150-158 (2010)
- [j167]Irith Pomeranz, Sudhakar M. Reddy: TOV: Sequential Test Generation by Ordering of Test Vectors. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 454-465 (2010)
- [j166]Irith Pomeranz, Sudhakar M. Reddy: On Test Generation With Test Vector Improvement. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 502-506 (2010)
- [j165]Irith Pomeranz, Sudhakar M. Reddy: On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 29(7): 1135-1140 (2010)
- [j164]Irith Pomeranz, Sudhakar M. Reddy: Hazard-Based Detection Conditions for Improved Transition Path Delay Fault Coverage. IEEE Trans. on CAD of Integrated Circuits and Systems 29(9): 1449-1453 (2010)
- [j163]Irith Pomeranz, Sudhakar M. Reddy: On Undetectable Faults and Fault Diagnosis. IEEE Trans. on CAD of Integrated Circuits and Systems 29(11): 1832-1837 (2010)
- [j162]Irith Pomeranz, Sudhakar M. Reddy: Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests. IEEE Trans. VLSI Syst. 18(2): 333-337 (2010)
- [j161]Irith Pomeranz, Sudhakar M. Reddy: Path Selection for Transition Path Delay Faults. IEEE Trans. VLSI Syst. 18(3): 401-409 (2010)
- [j160]Irith Pomeranz, Sudhakar M. Reddy: Robust Fault Models Where Undetectable Faults Imply Logic Redundancy. IEEE Trans. VLSI Syst. 18(8): 1230-1234 (2010)
- [j159]Irith Pomeranz, Sudhakar M. Reddy: Switching Activity as a Test Compaction Heuristic for Transition Faults. IEEE Trans. VLSI Syst. 18(9): 1357-1361 (2010)
- [j158]Irith Pomeranz, Sudhakar M. Reddy: Selection of a Fault Model for Fault Diagnosis Based on Unique Responses. IEEE Trans. VLSI Syst. 18(11): 1533-1543 (2010)
- [c350]Irith Pomeranz, Sudhakar M. Reddy: Functional and partially-functional skewed-load tests. ASP-DAC 2010: 505-510
- [c349]Xun Tang, Wu-Tung Cheng, Ruifeng Guo, Sudhakar M. Reddy: Diagnosis of Multiple Physical Defects Using Logic Fault Models. Asian Test Symposium 2010: 94-99
- [c348]Irith Pomeranz, Sudhakar M. Reddy: On Bias in Transition Coverage of Test Sets for Path Delay Faults. Asian Test Symposium 2010: 349-352
- [c347]Irith Pomeranz, Sudhakar M. Reddy: Reducing the storage requirements of a test sequence by using a background vector. DATE 2010: 1237-1242
- [c346]
- [c345]Irith Pomeranz, Sudhakar M. Reddy: Input test data volume reduction based on test vector chains. European Test Symposium 2010: 240
- [c344]Bo Yao, Irith Pomeranz, Sudhakar M. Reddy: Deterministic broadside test generation for transition path delay faults. ACM Great Lakes Symposium on VLSI 2010: 135-138
- [c343]Irith Pomeranz, Sudhakar M. Reddy: Selecting state variables for improved on-line testability through output response comparison of identical circuits. IOLTS 2010: 179-184
- [c342]Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab: Low capture power at-speed test in EDT environment. ITC 2010: 714-723
- [c341]Narendra Devta-Prasanna, Arun Gunda, Sudhakar M. Reddy, Irith Pomeranz: Multiple fault activation cycle tests for transistor stuck-open faults. ITC 2010: 821
- [c340]Irith Pomeranz, Sudhakar M. Reddy: Output-Dependent Diagnostic Test Generation. VLSI Design 2010: 3-8
- [c339]Irith Pomeranz, Sudhakar M. Reddy: Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration. VLSI Design 2010: 39-44
- [c338]Irith Pomeranz, Sudhakar M. Reddy: Forming multi-cycle tests for delay faults by concatenating broadside tests. VTS 2010: 51-56
- [c337]Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Mark Kassab: At-speed scan test with low switching activity. VTS 2010: 177-182
- [c336]
2000 – 2009
- 2009
- [j157]Irith Pomeranz, Sudhakar M. Reddy: Definition and generation of partially-functional broadside tests. IET Computers & Digital Techniques 3(1): 1-13 (2009)
- [j156]Irith Pomeranz, Sudhakar M. Reddy: Same/different fault dictionary: an extended pass/fail fault dictionary with improved diagnostic resolution. IET Computers & Digital Techniques 3(1): 85-93 (2009)
- [j155]Irith Pomeranz, Sudhakar M. Reddy: Test vector chains for increasing the fault coverage and numbers of detections. IET Computers & Digital Techniques 3(2): 222-233 (2009)
- [j154]Irith Pomeranz, Sudhakar M. Reddy: Test compaction methods for transition faults under transparent-scan. IET Computers & Digital Techniques 3(4): 315-328 (2009)
- [j153]Irith Pomeranz, Sudhakar M. Reddy: Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions. IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 121-129 (2009)
- [j152]S. Saqib Khursheed, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Peter Harrod: Diagnosis of Multiple-Voltage Design With Bridge Defect. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 406-416 (2009)
- [j151]Irith Pomeranz, Sudhakar M. Reddy: Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 426-432 (2009)
- [j150]Urban Ingelsson, Bashir M. Al-Hashimi, S. Saqib Khursheed, Sudhakar M. Reddy, Peter Harrod: Process Variation-Aware Test for Resistive Bridges. IEEE Trans. on CAD of Integrated Circuits and Systems 28(8): 1269-1274 (2009)
- [j149]Irith Pomeranz, Sudhakar M. Reddy: Forward-Looking Reverse Order Fault Simulation for n -Detection Test Sets. IEEE Trans. on CAD of Integrated Circuits and Systems 28(9): 1424-1428 (2009)
- [j148]Irith Pomeranz, Sudhakar M. Reddy: Semiconcurrent Online Testing of Transition Faults through Output Response Comparison of Identical Circuits. IEEE Trans. Dependable Sec. Comput. 6(3): 231-240 (2009)
- [j147]Irith Pomeranz, Sudhakar M. Reddy: Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits. ACM Trans. Design Autom. Electr. Syst. 15(1) (2009)
- [j146]Irith Pomeranz, Sudhakar M. Reddy: Random Test Generation With Input Cube Avoidance. IEEE Trans. VLSI Syst. 17(1): 45-54 (2009)
- [c335]Irith Pomeranz, Sudhakar M. Reddy: Dynamic test compaction for a random test generation procedure with input cube avoidance. ASP-DAC 2009: 672-677
- [c334]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz: Detectability of internal bridging faults in scan chains. ASP-DAC 2009: 678-683
- [c333]Irith Pomeranz, Sudhakar M. Reddy: Fault Diagnosis under Transparent-Scan. Asian Test Symposium 2009: 29-34
- [c332]Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy, Yu Huang: On Improving Diagnostic Test Generation for Scan Chain Failures. Asian Test Symposium 2009: 41-46
- [c331]Gang Chen, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz: N-distinguishing Tests for Enhanced Defect Diagnosis. Asian Test Symposium 2009: 183-186
- [c330]Alejandro Czutro, Ilia Polian, Piet Engelke, Sudhakar M. Reddy, Bernd Becker: Dynamic Compaction in SAT-Based ATPG. Asian Test Symposium 2009: 187-190
- [c329]Irith Pomeranz, Sudhakar M. Reddy: Selection of a fault model for fault diagnosis based on unique responses. DATE 2009: 994-999
- [c328]Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy: Improving compressed test pattern generation for multiple scan chain failure diagnosis. DATE 2009: 1000-1005
- [c327]Santiago Remersaro, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz: A scalable method for the generation of small test sets. DATE 2009: 1136-1141
- [c326]Irith Pomeranz, Sudhakar M. Reddy: On-chip Generation of the Second Primary Input Vectors of Broadside Tests. DFT 2009: 38-46
- [c325]Irith Pomeranz, Sudhakar M. Reddy: Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences. DFT 2009: 358-366
- [c324]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz: Improving the Detectability of Resistive Open Faults in Scan Cells. DFT 2009: 383-391
- [c323]Irith Pomeranz, Sudhakar M. Reddy: Input Cubes with Lingering Synchronization Effects and their Use in Random Sequential Test Generation. European Test Symposium 2009: 87-92
- [c322]Irith Pomeranz, Sudhakar M. Reddy: Partitioned n-detection test generation. ACM Great Lakes Symposium on VLSI 2009: 93-98
- [c321]Irith Pomeranz, Sudhakar M. Reddy: Definition and application of approximate necessary assignments. ACM Great Lakes Symposium on VLSI 2009: 105-108
- [c320]Irith Pomeranz, Sudhakar M. Reddy: State persistence: a property for guiding test generation. ACM Great Lakes Symposium on VLSI 2009: 523-528
- [c319]Aftab Farooqi, Richard O. Gale, Sudhakar M. Reddy, Brian Nutter, Chris Monico: Markov source based test length optimized SCAN-BIST architecture. ISQED 2009: 708-713
- [c318]Irith Pomeranz, Sudhakar M. Reddy: The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality. VLSI Design 2009: 215-220
- [c317]Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker: TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. VLSI Design 2009: 227-232
- 2008
- [j145]Kohei Miyase, Kenta Terashima, Xiaoqing Wen, Seiji Kajihara, Sudhakar M. Reddy: On Detection of Bridge Defects with Stuck-at Tests. IEICE Transactions 91-D(3): 683-689 (2008)
- [j144]Irith Pomeranz, Sudhakar M. Reddy: Functional Broadside Tests with Minimum and Maximum Switching Activity. J. Low Power Electronics 4(3): 429-437 (2008)
- [j143]Irith Pomeranz, Sudhakar M. Reddy: Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 137-146 (2008)
- [j142]Irith Pomeranz, Sudhakar M. Reddy: Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 193-197 (2008)
- [j141]Irith Pomeranz, Sudhakar M. Reddy: Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 398-403 (2008)
- [j140]Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy: On Complete Functional Broadside Tests for Transition Faults. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 583-587 (2008)
- [j139]Irith Pomeranz, Sudhakar M. Reddy: On the Saturation of n-Detection Test Generation by Different Definitions With Increased n. IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 946-957 (2008)
- [j138]Irith Pomeranz, Sudhakar M. Reddy: Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects. IEEE Trans. VLSI Syst. 16(1): 98-107 (2008)
- [j137]Irith Pomeranz, Sudhakar M. Reddy: Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion. IEEE Trans. VLSI Syst. 16(7): 931-936 (2008)
- [c316]Irith Pomeranz, Sudhakar M. Reddy: Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits. ASP-DAC 2008: 641-646
- [c315]Irith Pomeranz, Sudhakar M. Reddy: Test vector chains for increased targeted and untargeted fault coverage. ASP-DAC 2008: 663-666
- [c314]Sudhakar M. Reddy, Irith Pomeranz, Chen Liu: On tests to detect via opens in digital CMOS circuits. DAC 2008: 840-845
- [c313]Irith Pomeranz, Sudhakar M. Reddy: A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy. DATE 2008: 1166-1171
- [c312]Irith Pomeranz, Sudhakar M. Reddy: A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution. DATE 2008: 1474-1479
- [c311]Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, Xun Tang, Bernd Becker: On Reducing Circuit Malfunctions Caused by Soft Errors. DFT 2008: 245-253
- [c310]Santiago Remersaro, Janusz Rajski, Thomas Rinderknecht, Sudhakar M. Reddy, Irith Pomeranz: ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction. DFT 2008: 385-393
- [c309]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz: Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. DFT 2008: 394-402
- [c308]Irith Pomeranz, Sudhakar M. Reddy: Safe Fault Collapsing Based on Dominance Relations. European Test Symposium 2008: 7-12
- [c307]S. Saqib Khursheed, Paul M. Rosinger, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Peter Harrod: Bridge Defect Diagnosis for Multiple-Voltage Design. European Test Symposium 2008: 99-104
- [c306]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz: An Enhanced Logic BIST Architecture for Online Testing. IOLTS 2008: 10-15
- [c305]Ilia Polian, Sudhakar M. Reddy, Bernd Becker: Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. ISVLSI 2008: 257-262
- [c304]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz: Detection of Internal Stuck-open Faults in Scan Chains. ITC 2008: 1-10
- [c303]Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu: On Common-Mode Skewed-Load and Broadside Tests. VLSI Design 2008: 151-156
- [c302]Irith Pomeranz, Sudhakar M. Reddy: Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths. VLSI Design 2008: 175-180
- [c301]Irith Pomeranz, Sudhakar M. Reddy: Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity. VLSI Design 2008: 181-186
- [c300]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz: On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. VTS 2008: 79-84
- [c299]Irith Pomeranz, Sudhakar M. Reddy: Synthesis for Broadside Testability of Transition Faults. VTS 2008: 221-226
- [c298]Irith Pomeranz, Sudhakar M. Reddy: Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests. VTS 2008: 317-322
- 2007
- [j136]Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski: Scan-Based Tests with Low Switching Activity. IEEE Design & Test of Computers 24(3): 268-275 (2007)
- [j135]Irith Pomeranz, Sudhakar M. Reddy: On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits. Electr. Notes Theor. Comput. Sci. 174(4): 83-93 (2007)
- [j134]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi: Enhancing delay fault coverage through low-power segmented scan. IET Computers & Digital Techniques 1(3): 220-229 (2007)
- [j133]Irith Pomeranz, Sudhakar M. Reddy: Worst-case and average-case analysis of n-detection test sets and test generation strategies. IET Computers & Digital Techniques 1(4): 353-363 (2007)
- [j132]Irith Pomeranz, Sudhakar M. Reddy: Effectiveness of scan-based delay fault tests in diagnosis of transition faults. IET Computers & Digital Techniques 1(5): 537-545 (2007)
- [j131]Irith Pomeranz, Sudhakar M. Reddy: Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1311-1319 (2007)
- [j130]Irith Pomeranz, Sudhakar M. Reddy, Srikanth Venkataraman: z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1700-1712 (2007)
- [j129]Yuan Cai, Marcus T. Schmitz, Bashir M. Al-Hashimi, Sudhakar M. Reddy: Workload-ahead-driven online energy minimization techniques for battery-powered embedded systems with time-constraints. ACM Trans. Design Autom. Electr. Syst. 12(1) (2007)
- [j128]Irith Pomeranz, Sudhakar M. Reddy: Forming N-detection test sets without test generation. ACM Trans. Design Autom. Electr. Syst. 12(2) (2007)
- [c297]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz: Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes. ASP-DAC 2007: 817-822
- [c296]
- [c295]
- [c294]Irith Pomeranz, Sudhakar M. Reddy: Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits. DFT 2007: 457-455
- [c293]Irith Pomeranz, Sudhakar M. Reddy: Diagnostic Test Generation Based on Subsets of Faults. European Test Symposium 2007: 151-158
- [c292]Yuan Cai, Sudhakar M. Reddy, Bashir M. Al-Hashimi: Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-Constraint. ISQED 2007: 368-373
- [c291]Chen Liu, Wei Zou, Sudhakar M. Reddy, Wu-Tung Cheng, Manish Sharma, Huaxing Tang: Interconnect open defect diagnosis with minimal physical information. ITC 2007: 1-10
- [c290]Irith Pomeranz, Sudhakar M. Reddy: On the saturation of n-detection test sets with increased n. ITC 2007: 1-10
- [c289]Manish Sharma, Wu-Tung Cheng, Ting-Pu Tai, Y. S. Cheng, Will Hsu, Chen Liu, Sudhakar M. Reddy, Albert Mann: Faster defect localization in nanometer technology based on defective cell diagnosis. ITC 2007: 1-10
- [c288]Irith Pomeranz, Sudhakar M. Reddy: Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis. VLSI Design 2007: 498-503
- [c287]Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski: Low Shift and Capture Power Scan Tests. VLSI Design 2007: 793-798
- [c286]Irith Pomeranz, Sudhakar M. Reddy: Functional Broadside Tests with Different Levels of Reachability. VLSI Design 2007: 799-804
- [c285]Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang: Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary. VTS 2007: 225-230
- [c284]Irith Pomeranz, Sudhakar M. Reddy: Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs. VTS 2007: 416-421
- [i2]Irith Pomeranz, Sudhakar M. Reddy: The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits. CoRR abs/0710.4637 (2007)
- [i1]Irith Pomeranz, Sudhakar M. Reddy: Worst-Case and Average-Case Analysis of n-Detection Test Sets. CoRR abs/0710.4735 (2007)
- 2006
- [j127]Irith Pomeranz, Sudhakar M. Reddy: On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan. IEEE Trans. Computers 55(4): 491-495 (2006)
- [j126]Irith Pomeranz, Sudhakar M. Reddy: Scan-BIST based on transition probabilities for circuits with single and multiple scan chains. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 591-596 (2006)
- [j125]Irith Pomeranz, Sudhakar M. Reddy: Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1170-1175 (2006)
- [j124]Irith Pomeranz, Sudhakar M. Reddy: Generation of Functional Broadside Tests for Transition Faults. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2207-2218 (2006)
- [j123]Irith Pomeranz, Sudhakar M. Reddy: Using Dummy Bridging Faults to Define Reduced Sets of Target Faults. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2219-2227 (2006)
- [j122]Irith Pomeranz, Sudhakar M. Reddy: Improved n-Detection Test Sequences Under Transparent Scan. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2492-2501 (2006)
- [c283]Yuan Cai, Marcus T. Schmitz, Alireza Ejlali, Bashir M. Al-Hashimi, Sudhakar M. Reddy: Cache size selection for performance, energy and reliability of time-constrained systems. ASP-DAC 2006: 923-928
- [c282]Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski: A test pattern ordering algorithm for diagnosis with truncated fail data. DAC 2006: 399-404
- [c281]Irith Pomeranz, Sudhakar M. Reddy: Generation of broadside transition fault test sets that detect four-way bridging faults. DATE 2006: 907-912
- [c280]Irith Pomeranz, Sudhakar M. Reddy: Test compaction for transition faults under transparent-scan. DATE 2006: 1264-1269
- [c279]Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz: Test Generation for Open Defects in CMOS Circuits. DFT 2006: 41-49
- [c278]Irith Pomeranz, Sudhakar M. Reddy: Scan-Based Delay Fault Tests for Diagnosis of Transition Faults. DFT 2006: 419-427
- [c277]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi: Enhancing Delay Fault Coverage through Low Power Segmented Scan. European Test Symposium 2006: 21-28
- [c276]Irith Pomeranz, Sudhakar M. Reddy: Fault Collapsing for Transition Faults Using Extended Transition Faults. European Test Symposium 2006: 173-178
- [c275]Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz: A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults. European Test Symposium 2006: 185-192
- [c274]Irith Pomeranz, Sudhakar M. Reddy: A delay fault model for at-speed fault simulation and test generation. ICCAD 2006: 89-95
- [c273]Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz: A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST. IOLTS 2006: 37-42
- [c272]Irith Pomeranz, Sudhakar M. Reddy: Fault Detection by Output Response Comparison of Identical Circuits Using Half-Frequency Compatible Sequences. ITC 2006: 1-10
- [c271]Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski: Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. ITC 2006: 1-10
- [c270]Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang: On Methods to Improve Location Based Logic Diagnosis. VLSI Design 2006: 181-187
- [c269]Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski: New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic. VLSI Design 2006: 419-424
- [c268]Irith Pomeranz, Sudhakar M. Reddy: The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faults. VLSI Design 2006: 828-831
- [c267]Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy: A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults. VTS 2006: 294-299
- [c266]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski: Scan Tests with Multiple Fault Activation Cycles for Delay Faults. VTS 2006: 343-348
- [c265]Bharath Seshadri, Irith Pomeranz, Srikanth Venkataraman, Enamul Amyeen, Sudhakar M. Reddy: Dominance Based Analysis for Large Volume Production Fail Diagnosis. VTS 2006: 392-399
- 2005
- [j121]Irith Pomeranz, Sudhakar M. Reddy: On masking of redundant faults in synchronous sequential circuits with design-for-testability logic. IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 288-294 (2005)
- [j120]Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy: Finite memory test response compactors for embedded test applications. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 622-634 (2005)
- [j119]Irith Pomeranz, Sudhakar M. Reddy: On fault equivalence, fault dominance, and incompletely specified test sets. IEEE Trans. on CAD of Integrated Circuits and Systems 24(8): 1271-1274 (2005)
- [j118]Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy: On reducing test application time for scan circuits using limited scan operations and transfer sequences. IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1594-1605 (2005)
- [j117]Irith Pomeranz, Sudhakar M. Reddy: Concurrent Online Testing of Identical Circuits Using Nonidentical Input Vectors. IEEE Trans. Dependable Sec. Comput. 2(3): 190-200 (2005)
- [j116]Irith Pomeranz, Sudhakar M. Reddy: Autoscan: a scan design without external scan inputs or outputs. IEEE Trans. VLSI Syst. 13(9): 1087-1095 (2005)
- [c264]Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz: Circuit Independent Weighted Pseudo-Random BIST Pattern Generator. Asian Test Symposium 2005: 132-137
- [c263]Narendra Devta-Prasanna, Sudhakar M. Reddy, Arun Gunda, P. Krishnamurthy, Irith Pomeranz: Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions. Asian Test Symposium 2005: 202-207
- [c262]Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy: On Improving Defect Coverage of Stuck-at Fault Tests. Asian Test Symposium 2005: 216-223
- [c261]Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy: Bridge Defect Diagnosis with Physical Information. Asian Test Symposium 2005: 248-253
- [c260]Irith Pomeranz, Sudhakar M. Reddy: Worst-Case and Average-Case Analysis of n-Detection Test Sets. DATE 2005: 444-449
- [c259]Huaxing Tang, Gang Chen, Sudhakar M. Reddy, Chen Wang, Janusz Rajski, Irith Pomeranz: Defect Aware Test Patterns. DATE 2005: 450-455
- [c258]Irith Pomeranz, Sudhakar M. Reddy: The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits. DATE 2005: 1008-1013
- [c257]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz: On Generating Pseudo-Functional Delay Fault Tests for Scan Designs. DFT 2005: 398-405
- [c256]Irith Pomeranz, Sudhakar M. Reddy: Recovery During Concurrent On-Line Testing of Identical Circuits. DFT 2005: 475-483
- [c255]Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz: A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals. ICCD 2005: 471-474
- [c254]Yuan Cai, Sudhakar M. Reddy, Irith Pomeranz, Bashir M. Al-Hashimi: Battery-aware dynamic voltage scaling in multiprocessor embedded system. ISCAS (1) 2005: 616-619
- [c253]
- [c252]Wei Li, Sudhakar M. Reddy, Irith Pomeranz: On Reducing Peak Current and Power during Test. ISVLSI 2005: 156-161
- [c251]Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy: Fault Diagnosis and Fault Model Aliasing. ISVLSI 2005: 206-211
- [c250]Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, Sudhakar M. Reddy: Full-speed field-programmable memory BIST architecture. ITC 2005: 9
- [c249]Irith Pomeranz, Sudhakar M. Reddy: Forming N-detection test sets from one-detection test sets without test generation. ITC 2005: 9
- [c248]Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz: Methods for improving transition delay fault coverage using broadside tests. ITC 2005: 10
- [c247]Irith Pomeranz, Sudhakar M. Reddy: Tuple Detection for Path Delay Faults: A Method for Improving Test Set Quality. VLSI Design 2005: 41-46
- [c246]Huaxing Tang, Chen Wang, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz: On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. VLSI Design 2005: 59-64
- [c245]Wei Li, Seongmoon Wang, Srimat T. Chakradhar, Sudhakar M. Reddy: Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage. VLSI Design 2005: 471-478
- 2004
- [j115]Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy: Don't Care Identification and Statistical Encoding for Test Data Compression. IEICE Transactions 87-D(3): 544-550 (2004)
- [j114]Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy: Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units. IEEE Trans. Computers 53(1): 83-88 (2004)
- [j113]Irith Pomeranz, Sudhakar M. Reddy: On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit. IEEE Trans. Computers 53(9): 1121-1133 (2004)
- [j112]Irith Pomeranz, Sudhakar M. Reddy: A Measure of Quality for n-Detection Test Sets. IEEE Trans. Computers 53(11): 1497-1503 (2004)
- [j111]Irith Pomeranz, Sudhakar M. Reddy: Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests. IEEE Trans. Computers 53(12): 1569-1581 (2004)
- [j110]Irith Pomeranz, Sudhakar M. Reddy: Vector-restoration-based static compaction using random initial omission. IEEE Trans. on CAD of Integrated Circuits and Systems 23(11): 1587-1592 (2004)
- [j109]Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu: On the characterization and efficient computation of hard-to-detect bridging faults. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1640-1649 (2004)
- [j108]Irith Pomeranz, Sudhakar M. Reddy: Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. IEEE Trans. VLSI Syst. 12(7): 780-788 (2004)
- [c244]Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy: Multiple Scan Tree Design with Test Vector Modification. Asian Test Symposium 2004: 76-81
- [c243]Irith Pomeranz, Sudhakar M. Reddy: Properties of Maximally Dominating Faults. Asian Test Symposium 2004: 106-111
- [c242]Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz: Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults. Asian Test Symposium 2004: 178-183
- [c241]Irith Pomeranz, Sudhakar M. Reddy: A Postprocessing Procedure of Test Enrichment for Path Delay Faults. Asian Test Symposium 2004: 448-453
- [c240]Wei Li, Sudhakar M. Reddy, Irith Pomeranz: On test generation for transition faults with minimized peak power dissipation. DAC 2004: 504-509
- [c239]Irith Pomeranz, Sudhakar M. Reddy: Level of Similarity: A Metric for Fault Collapsing. DATE 2004: 56-61
- [c238]Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, Bharath Seshadri: Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis. DATE 2004: 68-75
- [c237]Irith Pomeranz, Sudhakar M. Reddy: Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines. DFT 2004: 183-190
- [c236]Irith Pomeranz, Sudhakar M. Reddy: Concurrent On-Line Testing of Identical Circuits Through Output Comparison Using Non-Identical Input Vectors. DFT 2004: 469-476
- [c235]Irith Pomeranz, Sudhakar M. Reddy: On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan. ICCD 2004: 82-84
- [c234]Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy: Test Application Time Reduction for Scan Circuits Using Limited Scan Operations. ISQED 2004: 211-216
- [c233]Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy: Scan BIST Targeting Transition Faults Using a Markov Source. ISQED 2004: 497-502
- [c232]Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy: Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection. ITC 2004: 489-497
- [c231]Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, Enamul Amyeen: Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults. VLSI Design 2004: 475-480
- [c230]Irith Pomeranz, Sudhakar M. Reddy: On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data Compression. VLSI Design 2004: 741-744
- [c229]Xiaogang Du, Sudhakar M. Reddy, Wu-Tung Cheng, Joseph Rayhawk, Nilanjan Mukherjee: At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories. VLSI Design 2004: 895-900
- [c228]Xiaogang Du, Sudhakar M. Reddy, Don E. Ross, Wu-Tung Cheng, Joseph Rayhawk: Memory BIST Using ESP. VTS 2004: 243-248
- 2003
- [j107]Yun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara: On Selecting Testable Paths in Scan Designs. J. Electronic Testing 19(4): 447-456 (2003)
- [j106]Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz: A Low Power Pseudo-Random BIST Technique. J. Electronic Testing 19(6): 637-644 (2003)
- [j105]Irith Pomeranz, Sudhakar M. Reddy: Test enrichment for path delay faults using multiple sets of target faults. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 82-90 (2003)
- [j104]Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz: Reverse-order-restoration-based static test compaction for synchronous sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 293-304 (2003)
- [j103]Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz: PROPTEST: a property-based test generator for synchronous sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 1080-1091 (2003)
- [j102]Irith Pomeranz, Sudhakar M. Reddy: Theorems for identifying undetectable faults in partial-scan circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 1092-1097 (2003)
- [j101]Irith Pomeranz, Sudhakar M. Reddy: Test data compression based on input-output dependence. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1450-1455 (2003)
- [j100]Irith Pomeranz, Sudhakar M. Reddy: Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations. IEEE Trans. on CAD of Integrated Circuits and Systems 22(12): 1663-1670 (2003)
- [j99]Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz: On test data volume reduction for multiple scan chain designs. ACM Trans. Design Autom. Electr. Syst. 8(4): 460-469 (2003)
- [c227]Irith Pomeranz, Sudhakar M. Reddy: A DFT Approach for Path Delay Faults in Interconnected Circuits. Asian Test Symposium 2003: 72-77
- [c226]Xiaogang Du, Sudhakar M. Reddy, Joseph Rayhawk, Wu-Tung Cheng: Testing Delay Faults in Embedded CAMs. Asian Test Symposium 2003: 378-383
- [c225]Irith Pomeranz, Sudhakar M. Reddy: Test Data Volume Reduction by Test Data Realignment. Asian Test Symposium 2003: 434-439
- [c224]Wei Li, Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz: A scan BIST generation method using a markov source and partial bit-fixing. DAC 2003: 554-559
- [c223]Irith Pomeranz, Sudhakar M. Reddy: On test data compression and n-detection test sets. DAC 2003: 748-751
- [c222]Irith Pomeranz, Sudhakar M. Reddy: A New Approach to Test Generation and Test Compaction for Scan Circuits. DATE 2003: 11000-11005
- [c221]Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu: On the Characterization of Hard-to-Detect Bridging Faults. DATE 2003: 11012-11019
- [c220]Ilia Polian, Bernd Becker, Sudhakar M. Reddy: Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST. DATE 2003: 11184-11185
- [c219]Irith Pomeranz, Sudhakar M. Reddy: Test Data Compression Based on Output Dependence. DATE 2003: 11186-11187
- [c218]Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Jerzy Tyszer: On Compacting Test Response Data Containing Unknown Values. ICCAD 2003: 855-862
- [c217]Irith Pomeranz, Sudhakar M. Reddy: On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic. ICCAD 2003: 867-873
- [c216]Gang Chen, Sudhakar M. Reddy, Irith Pomeranz: Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits. ICCD 2003: 36-41
- [c215]Irith Pomeranz, Sudhakar M. Reddy: Static Test Compaction for Multiple Full-Scan Circuits. ICCD 2003: 393-396
- [c214]Chaowen Yu, Wei Li, Sudhakar M. Reddy, Irith Pomeranz: An Improved Markov Source Design for Scan BIST. IOLTS 2003: 106-110
- [c213]Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Sudhakar M. Reddy: Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. ISQED 2003: 99-104
- [c212]Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-Ju Hsieh, Yu-Ting Hung: Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault. ITC 2003: 319-328
- [c211]Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy: Convolutional Compaction of Test Responses. ITC 2003: 745-754
- [c210]Masao Naruse, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu: On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding. ITC 2003: 1060-1068
- [c209]Huaxing Tang, Sudhakar M. Reddy, Irith Pomeranz: On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs. ITC 2003: 1079-1088
- [c208]Wei Zou, Chris Chu, Sudhakar M. Reddy, Irith Pomeranz: Optimizing SOC Test Resources using Dual Sequences. VLSI-SOC 2003: 180-185
- [c207]Irith Pomeranz, Sudhakar M. Reddy: Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences. VLSI Design 2003: 335-340
- [c206]Ganesh Venkataraman, Sudhakar M. Reddy, Irith Pomeranz: GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment. VLSI Design 2003: 533-538
- [c205]Janak H. Patel, Steven S. Lumetta, Sudhakar M. Reddy: Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns. VTS 2003: 107-112
- [c204]Irith Pomeranz, Sudhakar M. Reddy: On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit. VTS 2003: 173-178
- [c203]Wei Zou, Sudhakar M. Reddy, Irith Pomeranz, Yu Huang: SOC Test Scheduling Using Simulated Annealing. VTS 2003: 325-330
- [c202]Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian: A Test Interface for Built-In Test of Non-Isolated Scanned Cores. VTS 2003: 371-378
- 2002
- [j98]Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy: Synthesis of Scan Chains for Netlist Descriptions at RT-Level. J. Electronic Testing 18(2): 189-201 (2002)
- [j97]Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy: On Concurrent Test of Core-Based SOC Design. J. Electronic Testing 18(4-5): 401-414 (2002)
- [j96]Irith Pomeranz, Sudhakar M. Reddy: Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times. IEEE Trans. Computers 51(4): 409-419 (2002)
- [j95]Irith Pomeranz, Sudhakar M. Reddy: Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission. IEEE Trans. Computers 51(7): 866-872 (2002)
- [j94]Irith Pomeranz, Sudhakar M. Reddy: A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set. IEEE Trans. Computers 51(11): 1282-1293 (2002)
- [j93]Irith Pomeranz, Sudhakar M. Reddy: Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults. IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 628-637 (2002)
- [j92]Irith Pomeranz, Sudhakar M. Reddy: Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences. IEEE Trans. on CAD of Integrated Circuits and Systems 21(6): 706-714 (2002)
- [j91]Irith Pomeranz, Sudhakar M. Reddy: n-pass n-detection fault simulation and its applications. IEEE Trans. on CAD of Integrated Circuits and Systems 21(8): 980-986 (2002)
- [c201]Yun Shao, Irith Pomeranz, Sudhakar M. Reddy: On Generating High Quality Tests for Transition Faults. Asian Test Symposium 2002: 1
- [c200]Irith Pomeranz, Sudhakar M. Reddy: Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences. Asian Test Symposium 2002: 61-66
- [c199]Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy: Test Data Compression Using Don?t-Care Identification and Statistical Encoding. Asian Test Symposium 2002: 67-
- [c198]Irith Pomeranz, Sudhakar M. Reddy: A Partitioning and Storage Based Built-In Test Pattern Generation Method for Delay Faults in Scan Circuits. Asian Test Symposium 2002: 110-115
- [c197]Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng: Core - Clustering Based SOC Test Scheduling Optimization. Asian Test Symposium 2002: 405-410
- [c196]Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy: On output response compression in the presence of unknown output values. DAC 2002: 255-258
- [c195]Irith Pomeranz, Sudhakar M. Reddy: Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults. DATE 2002: 722-729
- [c194]Irith Pomeranz, Janusz Rajski, Sudhakar M. Reddy: Finding a Common Fault Response for Diagnosis during Silicon Debug. DATE 2002: 1116
- [c193]Irith Pomeranz, Sudhakar M. Reddy: Properties of Output Sequences and their Use in Guiding Property-Based Test Generation for Synchronous Sequential Circuits. DELTA 2002: 377-381
- [c192]Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy: A Method of Static Test Compaction Based on Don't Care Identification. DELTA 2002: 392-395
- [c191]Seiji Kajihara, Kenjiro Taniguchi, Irith Pomeranz, Sudhakar M. Reddy: Test Data Compression Using Don't-Care Identification and Statistical Encoding. DELTA 2002: 413-416
- [c190]Irith Pomeranz, Sudhakar M. Reddy: On undetectable faults in partial scan circuits. ICCAD 2002: 82-86
- [c189]Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski: Conflict driven techniques for improving deterministic test pattern generation. ICCAD 2002: 87-93
- [c188]Kohei Miyase, Seiji Kajihara, Irith Pomeranz, Sudhakar M. Reddy: Don't-Care Identification on Specific Bits of Test Patterns. ICCD 2002: 194-199
- [c187]Irith Pomeranz, Sudhakar M. Reddy: On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains. ICCD 2002: 206-209
- [c186]Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz: A Low Power Pseudo-Random BIST Technique. ICCD 2002: 468-473
- [c185]Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz: A Low Power Pseudo-Random BIST Technique. IOLTW 2002: 140-
- [c184]Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan: Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. ITC 2002: 74-82
- [c183]Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita: On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. ITC 2002: 83-89
- [c182]Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz: Pseudo Random Patterns Using Markov Sources for Scan BIST. ITC 2002: 1013-1021
- [c181]Yu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy: Constraint Driven Pin Mapping for Concurrent SOC Testing. VLSI Design 2002: 511-516
- [c180]Nadir Z. Basturkmen, Sudhakar M. Reddy, Janusz Rajski: Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST. VLSI Design 2002: 604-
- [c179]Irith Pomeranz, Sudhakar M. Reddy: A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits. VLSI Design 2002: 677-682
- [c178]Yun Shao, Irith Pomeranz, Sudhakar M. Reddy: Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples. VLSI Design 2002: 767-772
- [c177]Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz: On Test Data Volume Reduction for Multiple Scan Chain Designs. VTS 2002: 103-110
- 2001
- [j90]Irith Pomeranz, Sudhakar M. Reddy: Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits. Journal of Systems Architecture 47(3-4): 357-373 (2001)
- [j89]Irith Pomeranz, Sudhakar M. Reddy: Vector replacement to improve static-test compaction forsynchronous sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 336-342 (2001)
- [j88]Irith Pomeranz, Sudhakar M. Reddy: On diagnosis and diagnostic test generation for pattern-dependenttransition faults. IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 791-800 (2001)
- [j87]Irith Pomeranz, Sudhakar M. Reddy: Forward-looking fault simulation for improved static compaction. IEEE Trans. on CAD of Integrated Circuits and Systems 20(10): 1262-1265 (2001)
- [j86]Irith Pomeranz, Sudhakar M. Reddy: A built-in self-test method for diagnosis of synchronous sequential circuits. IEEE Trans. VLSI Syst. 9(2): 290-296 (2001)
- [j85]Irith Pomeranz, Sudhakar M. Reddy: Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units. IEEE Trans. VLSI Syst. 9(5): 679-689 (2001)
- [c176]Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz: On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits. Asian Test Symposium 2001: 82-
- [c175]Irith Pomeranz, Sudhakar M. Reddy: A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan Circuits. Asian Test Symposium 2001: 131-136
- [c174]Yun Shao, Sudhakar M. Reddy, Seiji Kajihara, Irith Pomeranz: An Efficient Method to Identify Untestable Path Delay Faults. Asian Test Symposium 2001: 233-238
- [c173]Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy: Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. Asian Test Symposium 2001: 265-
- [c172]Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin: Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan. Asian Test Symposium 2001: 467
- [c171]Irith Pomeranz, Sudhakar M. Reddy: An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing. DAC 2001: 156-161
- [c170]Irith Pomeranz, Sudhakar M. Reddy: Sequence reordering to improve the levels of compaction achievable by static compaction procedures. DATE 2001: 214-218
- [c169]Irith Pomeranz, Sudhakar M. Reddy: Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage. DATE 2001: 504-508
- [c168]Irith Pomeranz, Sudhakar M. Reddy: ITEM: an iterative improvement test generation procedure for synchronous sequential circuits. ACM Great Lakes Symposium on VLSI 2001: 13-18
- [c167]Irith Pomeranz, Sudhakar M. Reddy: Estimating the relative single stuck-at fault coverage of test sets for a combinational logic block from its functional description. HLDVT 2001: 31-35
- [c166]Chen Wang, Irith Pomeranz, Sudhakar M. Reddy: REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits. ICCAD 2001: 370-374
- [c165]Irith Pomeranz, Sudhakar M. Reddy: COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction. ICCD 2001: 142-147
- [c164]Irith Pomeranz, Sudhakar M. Reddy: A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuits. ICCD 2001: 148-153
- [c163]Irith Pomeranz, Sudhakar M. Reddy: A method to enhance the fault coverage obtained by output response comparison of identical circuits. ITC 2001: 196-203
- [c162]Irith Pomeranz, Sudhakar M. Reddy: On improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. ITC 2001: 211-220
- [c161]Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Dan Devries, Wu-Tung Cheng, Sudhakar M. Reddy: On RTL scan design. ITC 2001: 728-737
- [c160]Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy: On static test compaction and test pattern ordering for scan designs. ITC 2001: 1088-1097
- [c159]Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy: On Improving Static Test Compaction for Sequential Circuits. VLSI Design 2001: 111-116
- [c158]Irith Pomeranz, Sudhakar M. Reddy: On the Use of Fault Dominance in n-Detection Test Generation. VTS 2001: 352-357
- 2000
- [j84]Irith Pomeranz, Sudhakar M. Reddy: Static Test Compaction for Scan-Based Designs to Reduce Test Application Time. J. Electronic Testing 16(5): 541-552 (2000)
- [j83]Irith Pomeranz, Sudhakar M. Reddy: On Finding a Minimal Functional Description of a Finite-State Machine for Test Generation for Adjacent Machines. IEEE Trans. Computers 49(1): 88-94 (2000)
- [j82]Irith Pomeranz, Sudhakar M. Reddy: On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits. IEEE Trans. Computers 49(2): 175-181 (2000)
- [j81]Irith Pomeranz, Sudhakar M. Reddy: Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits. IEEE Trans. Computers 49(6): 596-607 (2000)
- [j80]Irith Pomeranz, Sudhakar M. Reddy: On n-detection test sets and variable n-detection test sets fortransition faults. IEEE Trans. on CAD of Integrated Circuits and Systems 19(3): 372-383 (2000)
- [j79]Irith Pomeranz, Sudhakar M. Reddy: A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 589-600 (2000)
- [j78]Irith Pomeranz, Sudhakar M. Reddy: On synchronizable circuits and their synchronizing sequences. IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 1086-1092 (2000)
- [c157]Irith Pomeranz, Sudhakar M. Reddy: On the feasibility of fault simulation using partial circuit descriptions. Asian Test Symposium 2000: 108-113
- [c156]Seiji Kajihara, Takashi Shimono, Irith Pomeranz, Sudhakar M. Reddy: Enhanced untestable path analysis using edge graphs. Asian Test Symposium 2000: 139-144
- [c155]Irith Pomeranz, Sudhakar M. Reddy: Reducing test application time for full scan circuits by the addition of transfer sequences. Asian Test Symposium 2000: 317-322
- [c154]
- [c153]
- [c152]Irith Pomeranz, Sudhakar M. Reddy: Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits. DATE 2000: 298-304
- [c151]Irith Pomeranz, Sudhakar M. Reddy: Functional Test Generation for Full Scan Circuits. DATE 2000: 396-401
- [c150]Irith Pomeranz, Sudhakar M. Reddy: Test-Point Insertion to Enhance Test Compaction for Scan Designs. DSN 2000: 375-381
- [c149]Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski: Improving the Proportion of At-Speed Tests in Scan BIST. ICCAD 2000: 459-463
- [c148]Irith Pomeranz, Sudhakar M. Reddy: Simulation Based Test Generation for Scan Designs. ICCAD 2000: 544-549
- [c147]Irith Pomeranz, Sudhakar M. Reddy: Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation. ICCD 2000: 389-394
- [c146]Irith Pomeranz, Sudhakar M. Reddy: On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs. ICCD 2000: 395-
- [c145]Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta: On validating data hold times for flip-flops in sequential circuits. ITC 2000: 317-325
- [c144]Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy: Selection of potentially testable path delay faults for test generation. ITC 2000: 376-384
- [c143]Irith Pomeranz, Sudhakar M. Reddy: Fault diagnosis based on parameters of output responses. PRDC 2000: 139-147
- [c142]Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy: Test Transformation to Improve Compaction by Statistical Encoding. VLSI Design 2000: 294-299
- [c141]Irith Pomeranz, Sudhakar M. Reddy: On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits. VLSI Design 2000: 392-397
- [c140]Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy: SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. VTS 2000: 205-212
1990 – 1999
- 1999
- [j77]Irith Pomeranz, Sudhakar M. Reddy: A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n-Detections in Combinational Circuits. IEEE Trans. Computers 48(10): 1145-1152 (1999)
- [j76]Irith Pomeranz, Sudhakar M. Reddy: A comment on "Improving a nonenumerative method to estimate path delay fault coverage". IEEE Trans. on CAD of Integrated Circuits and Systems 18(5): 665-666 (1999)
- [j75]Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo: Static test compaction for synchronous sequential circuits based on vector restoration. IEEE Trans. on CAD of Integrated Circuits and Systems 18(7): 1040-1049 (1999)
- [j74]Uwe Sparmann, H. Mueller, Sudhakar M. Reddy: Universal delay test sets for logic networks. IEEE Trans. VLSI Syst. 7(2): 156-166 (1999)
- [c139]Irith Pomeranz, Sudhakar M. Reddy: Vector-Based Functional Fault Models for Delay Faults. Asian Test Symposium 1999: 41-46
- [c138]Irith Pomeranz, Sudhakar M. Reddy: Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits. Asian Test Symposium 1999: 75-80
- [c137]