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Shaolei Quan
2010 – today
- 2011
[j1]Freeman Zhong, Shaolei Quan, Wing Liu, Pervez M. Aziz, Tai Jing, Jen Dong, Chintan Desai, Hairong Gao, Monica Garcia, Gary Hom, Tony Huynh, Hiroshi Kimura, Ruchi Kothari, Lijun Li, Cathy Liu, Scott Lowrie, Kathy Ling, Amaresh V. Malipatil, Ram Narayan, Tom Prokop, Chaitanya Palusa, Anil Rajashekara, Ashutosh Sinha, Charlie Zhong, Eric Zhang: A 1.0625 ~ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS. J. Solid-State Circuits 46(12): 3126-3139 (2011)- [c6]Shaolei Quan, Freeman Zhong, Wing Liu, Pervez M. Aziz, Tai Jing, Jen Dong, Chintan Desai, Hairong Gao, Monica Garcia, Gary Hom, Tony Huynh, Hiroshi Kimura, Ruchi Kothari, Lijun Li, Cathy Liu, Scott Lowrie, Kathy Ling, Amaresh V. Malipatil, Ram Narayan, Tom Prokop, Chaitanya Palusa, Anil Rajashekara, Ashutosh Sinha, Charlie Zhong, Eric Zhang: A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS. ISSCC 2011: 348-350
2000 – 2009
- 2005
- [c5]Shaolei Quan, Qiang Qiang, Chin-Long Wey: Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test. Asian Test Symposium 2005: 70-75
- [c4]Shaolei Quan, Meng-Yao Liu, Chin-Long Wey: Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress. DFT 2005: 563-572
- [c3]Shaolei Quan, Qiang Qiang, Chin-Long Wey: A novel reconfigurable architecture of low-power unsigned multiplier for digital signal processing. ISCAS (4) 2005: 3327-3330
- 2004
- [c2]Shaolei Quan, Chin-Long Wey: A noise optimization technique for codesign of CMOS radio-frequency low noise amplifiers and low-quality spiral inductors. ACM Great Lakes Symposium on VLSI 2004: 178-182
- [c1]Cheong Kun, Shaolei Quan, Andrew Mason: A power-optimized 64-bit priority encoder utilizing parallel priority look-ahead. ISCAS (2) 2004: 753-756
Coauthor Index
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last updated on 2012-10-11 00:29 CEST by the dblp team