| 2012 | ||
|---|---|---|
| j4 | Stuart N. Wooters, Adam C. Cabe, Zhenyu Qi, Jiajing Wang, Randy W. Mann, Benton H. Calhoun, Mircea R. Stan, Travis N. Blalock: Tracking On-Chip Age Using Distributed, Embedded Sensors. IEEE Trans. VLSI Syst. 20(11): 1974-1985 (2012) | |
| 2010 | ||
| c20 | Jiajing Wang, Satyanand Nalam, Zhenyu Qi, Randy W. Mann, Mircea R. Stan, Benton H. Calhoun: Improving SRAM Vmin and yield by using variation-aware BTI stress. CICC 2010: 1-4 | |
| c19 | Adam C. Cabe, Zhenyu Qi, Mircea R. Stan: Stacking SRAM banks for ultra low power standby mode operation. DAC 2010: 699-704 | |
| c18 | Zhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun, Mircea R. Stan: SRAM-based NBTI/PBTI sensor system design. DAC 2010: 849-852 | |
| c17 | Zhenyu Qi, Brett H. Meyer, Wei Huang, Robert J. Ribando, Kevin Skadron, Mircea R. Stan: Temperature-to-power mapping. ICCD 2010: 384-389 | |
| 2009 | ||
| c16 | Adam C. Cabe, Zhenyu Qi, Stuart N. Wooters, Travis N. Blalock, Mircea R. Stan: Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay. ISQED 2009: 1-6 | |
| 2008 | ||
| c15 | Zhenyu Qi, Mircea R. Stan: NBTI resilient circuits using adaptive body biasing. ACM Great Lakes Symposium on VLSI 2008: 285-290 | |
| 2007 | ||
| c14 | Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu Qi, Mircea R. Stan: Structured and tuned array generation (STAG) for high-performance random logic. ACM Great Lakes Symposium on VLSI 2007: 257-262 | |
| c13 | Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan: Multi-Dimensional Circuit and Micro-Architecture Level Optimization. ISQED 2007: 275-280 | |
| c12 | ||
| 2006 | ||
| j3 | Zhenyu Qi, Hao Yu, Pu Liu, Sheldon X.-D. Tan, Lei He: Wideband passive multiport model order reduction and realization of RLCM circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1496-1509 (2006) | |
| j2 | Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong: Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2402-2412 (2006) | |
| c11 | Zhenyu Qi, Wei Huang, Adam C. Cabe, Wenqian Wu, Yan Zhang, Garrett S. Rose, Mircea R. Stan: A Design Methodology for a Low-Power, Temperature-Aware SoC Developed for Medical Image Processors. SoCC 2006: 111-112 | |
| 2005 | ||
| j1 | Sheldon X.-D. Tan, Weikun Guo, Zhenyu Qi: Hierarchical approach to exact symbolic analysis of large analog circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 24(8): 1241-1250 (2005) | |
| c10 | Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan: A wideband hierarchical circuit reduction for massively coupled interconnects. ASP-DAC 2005: 111-114 | |
| c9 | Zhenyu Qi, Sheldon X.-D. Tan, Hao Yu, Lei He: Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction. ASP-DAC 2005: 224-229 | |
| c8 | Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong: Partitioning-based approach to fast on-chip decap budgeting and minimization. DAC 2005: 170-175 | |
| c7 | Pu Liu, Zhenyu Qi, Hang Li, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang: Fast thermal simulation for architecture level dynamic thermal management. ICCAD 2005: 639-644 | |
| c6 | Pu Liu, Sheldon X.-D. Tan, Hang Li, Zhenyu Qi, Jun Kong, Bruce McGaughy, Lei He: An efficient method for terminal reduction of interconnect circuits considering delay variations. ICCAD 2005: 821-826 | |
| c5 | Hang Li, Pu Liu, Zhenyu Qi, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang: Efficient Thermal Simulation for Run-Time Temperature Tracking and Management. ICCD 2005: 130-136 | |
| c4 | Zhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong: Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery. ISQED 2005: 542-547 | |
| c3 | Pu Liu, Zhenyu Qi, Sheldon X.-D. Tan: Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits. ISQED 2005: 603-608 | |
| 2004 | ||
| c2 | Sheldon X.-D. Tan, Weikun Guo, Zhenyu Qi: Hierarchical approach to exact symbolic analysis of large analog circuits. DAC 2004: 860-863 | |
| c1 | Sheldon X.-D. Tan, Zhenyu Qi, Hang Li: Hierarchical Modeling and Simulation of Large Analog Circuits. DATE 2004: 740-741 | |
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