Mihalis Psarakis

Mihalis Psarakis, Andreas Apostolakis: Fault tolerant FPGA processor based on runtime reconfigurable modules. European Test Symposium 2012: 1-6

Mihalis Psarakis, Aggelos Pikrakis, Giannis Dendrinos: FPGA-based Acceleration for Tracking Audio Effects in Movies. FCCM 2012: 85-92

Jacques Henri Collet, Piotr Zajac, Mihalis Psarakis, Dimitris Gizopoulos: Chip Self-Organization and Fault Tolerance in Massively Defective Multicore Arrays. IEEE Trans. Dependable Sec. Comput. 8(2): 207-217 (2011)

Dimitris Gizopoulos, Mihalis Psarakis, Sarita V. Adve, Pradeep Ramachandran, Siva Kumar Sastry Hari, Daniel J. Sorin, Albert Meixner, A. Biswas, Xavier Vera: Architectures for online error detection and recovery in multicore processors. DATE 2011: 533-538

Aitzan Sari, Mihalis Psarakis: Scrubbing-based SEU mitigation approach for Systems-on-Programmable-Chips. FPT 2011: 1-8

Nikos Foutris, Dimitris Gizopoulos, Mihalis Psarakis, Xavier Vera, Antonio González: Accelerating microprocessor silicon validation by exposing ISA diversity. MICRO 2011: 386-397

Mihalis Psarakis, Dimitris Gizopoulos, Edgar E. Sánchez, Matteo Sonza Reorda: Microprocessor Software-Based Self-Testing. IEEE Design & Test of Computers 27(3): 4-19 (2010)

Nikos Foutris, Mihalis Psarakis, Dimitris Gizopoulos, Andreas Apostolakis, Xavier Vera, Antonio González: MT-SBST: Self-test optimization in multithreaded multicore architectures. ITC 2010: 734-743

Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Danilo Ravotto, Matteo Sonza Reorda: Test Program Generation for Communication Peripherals in Processor-Based SoC Devices. IEEE Design & Test of Computers 26(2): 52-63 (2009)

Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis: Software-Based Self-Testing of Symmetric Shared-Memory Multiprocessors. IEEE Trans. Computers 58(12): 1682-1694 (2009)

George Xenoulis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis: Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units. IEEE Trans. Dependable Sec. Comput. 6(2): 124-134 (2009)

Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Ishwar Parulkar: Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors. European Test Symposium 2009: 33-38

Eleftherios Kolonis, Michael Nicolaidis, Dimitris Gizopoulos, Mihalis Psarakis, Jacques Henri Collet, Piotr Zajac: Enhanced self-configurability and yield in multicore grids. IOLTS 2009: 75-80

Dimitris Gizopoulos, Mihalis Psarakis, Miltiadis Hatzimihail, M. Maniatakos, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi: Systematic Software-Based Self-Test for Pipelined Processors. IEEE Trans. VLSI Syst. 16(11): 1441-1453 (2008)

Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis: Functional Self-Testing for Bus-Based Symmetric Multiprocessors. DATE 2008: 1304-1309

Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis: Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip. IEEE Trans. VLSI Syst. 15(8): 971-975 (2007)

George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis: On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors. DFT 2007: 379-387

Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis: A Functional Self-Test Approach for Peripheral Cores in Processor-Based SoCs. IOLTS 2007: 271-276

Miltiadis Hatzimihail, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis: A methodology for detecting performance faults in microprocessors via performance monitoring hardware. ITC 2007: 1-10

George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis: Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units. IEEE Trans. Computers 55(11): 1449-1457 (2006)

Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi: Systematic software-based self-test for pipelined processors. DAC 2006: 393-398

P. Kenterlis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis: A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs. IOLTS 2006: 235-241

Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis: Built-in sequential fault self-testing of array multipliers. IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 449-460 (2005)

Miltiadis Hatzimihail, Mihalis Psarakis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis: Software-Based Self-Test for Pipelined Processors: A Case Study. DFT 2005: 535-543

George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis: Test Generation Methodology for High-Speed Floating Point Adders. IOLTS 2005: 227-232

Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian: Easily Testable Cellular Carry Lookahead Adders. J. Electronic Testing 19(3): 285-298 (2003)

Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis, Yervant Zorian: An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. J. Electronic Testing 17(2): 97-107 (2001)

Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Yervant Zorian: Deterministic software-based self-testing of embedded processor cores. DATE 2001: 92-96

Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. ISQED 2001: 343-349

Mihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian: Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers. VTS 2001: 15-21

Nektarios Kranitis, Dimitris Gizopoulos, Antonis M. Paschalis, Mihalis Psarakis, Yervant Zorian: Power-/Energy Efficient BIST Schemes for Processor Data Paths. IEEE Design & Test of Computers 17(4): 15-28 (2000)

Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays. IEEE Trans. Computers 49(10): 1083-1099 (2000)

Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian: Effective Low Power BIST for Datapaths. DATE 2000: 757

Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian: Low Power/Energy BIST Scheme for Datapaths. VTS 2000: 23-28

Antonis M. Paschalis, Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Yervant Zorian: An Effective BIST Architecture for Fast Multiplier Cores. DATE 1999: 117-121

Mihalis Psarakis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian: An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers. VTS 1999: 252-259

Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis: Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools. J. Electronic Testing 13(3): 315-319 (1998)

Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model. VTS 1998: 152-157

Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian, Mihalis Psarakis: An Effective BIST Scheme for Arithmetic Logic Units. ITC 1997: 868-877

Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis: Robust Sequential Fault Testing of Iterative Logic Arrays. VTS 1997: 238-244