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 | 2012 | |
|---|---|---|
| c128 |      | C. Zambelli, Marco Indaco, Michele Fabiano, Stefano Di Carlo, Paolo Prinetto, Piero Olivo, D. Bertozzi: A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories. DATE 2012: 881-886 |
| c127 | | Nadereh Hatami, Rafal Baranowski, Paolo Prinetto, Hans-Joachim Wunderlich: Efficient system-level aging prediction. European Test Symposium 2012: 1-6 |
| c126 | | Umar Shoaib, Nadeem Ahmad, Paolo Prinetto, Gabriele Tiotto: A platform-independent user-friendly dictionary from Italian to LIS. LREC 2012: 2435-2438 |
| 2011 | ||
| j42 | | Rafal Baranowski, Stefano Di Carlo, Nadereh Hatami, Michael E. Imhof, Michael A. Kochte, Paolo Prinetto, Hans-Joachim Wunderlich, Christian G. Zoellin: Efficient multi-level fault simulation of HW/SW systems for structural faults. SCIENCE CHINA Information Sciences 54(9): 1784-1796 (2011) |
| j41 | | Stefano Di Carlo, Paolo Prinetto, Alessandro Savino: Software-Based Self-Test of Set-Associative Cache Memories. IEEE Trans. Computers 60(7): 1030-1044 (2011) |
| c125 | | Davide Barberis, Nicola Garazzino, Paolo Prinetto, Gabriele Tiotto: Improving accessibility for deaf people: an editor for computer assisted translation through virtual avatars. ASSETS 2011: 253-254 |
| c124 | | Stefano Di Carlo, Giulio Gambardella, Marco Indaco, Daniele Rolfo, Paolo Prinetto: MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches. Asian Test Symposium 2011: 401-406 |
| c123 | | Stefano Di Carlo, Gianfranco Politano, Paolo Prinetto, Alessandro Savino, Alberto Scionti: Genetic Defect Based March Test Generation for SRAM. EvoApplications (2) 2011: 141-150 |
| c122 | | Stefano Di Carlo, Giulio Gambardella, Marco Indaco, Daniele Rolfo, Paolo Prinetto: A unifying formalism to support automated synthesis of SBSTs for embedded caches. EWDTS 2011: 39-42 |
| 2010 | ||
| c121 | | Michael A. Kochte, Christian G. Zoellin, Rafal Baranowski, Michael E. Imhof, Hans-Joachim Wunderlich, Nadereh Hatami, Stefano Di Carlo, Paolo Prinetto: Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level. Asian Test Symposium 2010: 3-8 |
| c120 | | Stefano Di Carlo, Andrea Miele, Paolo Prinetto, Antonio Trapanese: Microprocessor fault-tolerance via on-the-fly partial reconfiguration. European Test Symposium 2010: 201-206 |
| c119 | | Stefano Di Carlo, Michele Fabiano, Roberto Piazza, Paolo Prinetto: Exploring modeling and testing of NAND flash memories. EWDTS 2010: 47-50 |
| c118 | | Stefano Di Carlo, Michele Fabiano, Roberto Piazza, Paolo Prinetto: EDACs and test integration strategies for NAND flash memories. EWDTS 2010: 218-221 |
| c117 | | Nadereh Hatami, Marco Indaco, Paolo Prinetto, Gabriele Tiotto: Communication interface synthesis from TLM 2.0 to RTL. EWDTS 2010: 222-226 |
| c116 | | Nadereh Hatami, Paolo Prinetto, Gabriele Tiotto: Sign Language synthesis using hand motion acquisition. EWDTS 2010: 226-229 |
| c115 | | Homa Alemzadeh, Marco Cimei, Paolo Prinetto, Zainalabedin Navabi: Facilitating testability of TLM FIFO: SystemC implementations. EWDTS 2010: 428-431 |
| c114 | | Maurizio Caramia, Michele Fabiano, Andrea Miele, Roberto Piazza, Paolo Prinetto: Automated synthesis of EDACs for FLASH memories with user-selectable correction capability. HLDVT 2010: 113-120 |
| c113 | | Davide Barberis, Nicola Garazzino, Elio Piccolo, Paolo Prinetto, Gabriele Tiotto: A Web Based Platform for Sign Language Corpus Creation. ICCHP (2) 2010: 193-199 |
| c112 | | Michael A. Kochte, Christian G. Zoellin, Rafal Baranowski, Michael E. Imhof, Hans-Joachim Wunderlich, Nadereh Hatami, Stefano Di Carlo, Paolo Prinetto: System reliability evaluation using concurrent multi-level simulation of structural faults. ITC 2010: 817 |
| 2009 | ||
| j40 | | Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Paolo Prinetto: Are IEEE-1500-Compliant Cores Really Compliant to the Standard?. IEEE Design & Test of Computers 26(3): 16-24 (2009) |
| c111 | | Stefano Di Carlo, Paolo Prinetto, Alberto Scionti: A FPGA-Based Reconfigurable Software Architecture for Highly Dependable Systems. Asian Test Symposium 2009: 125-130 |
| c110 | | Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Rauf Salimi Khaligh, Martin Radetzki, Hans-Joachim Wunderlich, Stefano Di Carlo, Paolo Prinetto: Test exploration and validation using transaction level models. DATE 2009: 1250-1253 |
| c109 | | Stefano Di Carlo, Nadereh Hatami, Paolo Prinetto, Alessandro Savino: System Level Testing via TLM 2.0 Debug Transport Interface. DFT 2009: 286-294 |
| c108 | | Maurizio Caramia, Stefano Di Carlo, Michele Fabiano, Paolo Prinetto: FLARE: A design environment for FLASH-based space applications. HLDVT 2009: 14-19 |
| c107 | | Stefano Di Carlo, Nadereh Hatami, Paolo Prinetto: Test infrastructures evaluation at transaction level. ITC 2009: 1 |
| c106 | | Paolo Prinetto, Gabriele Tiotto, A. Del Principe: Designing health care applications for the deaf. PervasiveHealth 2009: 1-2 |
| 2008 | ||
| j39 | | Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: March Test Generation Revealed. IEEE Trans. Computers 57(12): 1704-1713 (2008) |
| j38 | | Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian: IEEE Standard 1500 Compliance Verification for Embedded Cores. IEEE Trans. VLSI Syst. 16(4): 397-407 (2008) |
| c105 | | Andrea Falletto, Paolo Prinetto, Gabriele Tiotto: An Avatar-Based Italian Sign Language Visualization System. eHealth 2008: 154-160 |
| c104 | | Simone Alpe, Stefano Di Carlo, Paolo Prinetto, Alessandro Savino: Applying March Tests to K-Way Set-Associative Cache Memories. European Test Symposium 2008: 77-83 |
| c103 | | Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi: An IEEE 1500 compatible wrapper architecture for testing cores at transaction level. EWDTS 2008: 178-181 |
| c102 | | Homa Alemzadeh, Zainalabedin Navabi, Stefano Di Carlo, Alberto Scionti, Paolo Prinetto: Functional testing approaches for "BIFST-able" tlm_fifo. HLDVT 2008: 85-92 |
| c101 | | Stefano Di Carlo, Paolo Prinetto, Alberto Scionti, Zaid Al-Ars: Automating defects simulation and fault modeling for SRAMs. HLDVT 2008: 169-176 |
| c100 | | Fatemeh Refan, Homa Alemzadeh, Saeed Safari, Paolo Prinetto, Zainalabedin Navabi: Reliability in Application Specific Mesh-Based NoC Architectures. IOLTS 2008: 207-212 |
| c99 | | Homa Alemzadeh, Stefano Di Carlo, Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi: "Plug & Test" at System Level via Testable TLM Primitives. ITC 2008: 1-10 |
| 2007 | ||
| j37 | | Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: March AB, a state-of-the-art march test for realistic static linked faults and dynamic faults in SRAMs. IET Computers & Digital Techniques 1(3): 237-245 (2007) |
| c98 | | Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Alberto Bosio: Automating the IEEE std.1500 compliance verification for embedded cores. HLDVT 2007: 171-178 |
| c97 | | Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale: Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. IOLTS 2007: 205-206 |
| 2006 | ||
| j36 | | Mark D. Hill, Jean-Luc Gaudiot, Mary W. Hall, Joe Marks, Paolo Prinetto, Donna Baglio: A Wiki for discussing and promoting best practices in research. Commun. ACM 49(9): 63-64 (2006) |
| c96 | | Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: Automatic march tests generations for static linked faults in SRAMs. DATE 2006: 1258-1263 |
| c95 |  | Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs. DDECS 2006: 157-158 |
| c94 | | Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: Automatic March Tests Generation for Multi-Port SRAMs. DELTA 2006: 385-392 |
| c93 | | Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto: Single-Event Upset Analysis and Protection in High Speed Circuits. European Test Symposium 2006: 29-34 |
| c92 | | Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: A 22n March Test for Realistic Static Linked Faults in SRAMs. European Test Symposium 2006: 49-54 |
| 2005 | ||
| j35 | | Andrea Baldini, Alfredo Benso, Paolo Prinetto: A Dependable Autonomic Computing Environment for Self-Testing of Complex Heterogeneous Systems. Electr. Notes Theor. Comput. Sci. 116: 47-57 (2005) |
| j34 | | Liviu Miclea, Szilárd Enyedi, Paolo Prinetto, Alfredo Benso: Agent-based test and repair of distributed systems. J. Embedded Computing 1(3): 405-414 (2005) |
| j33 | | Andrea Baldini, Alfredo Benso, Paolo Prinetto: System-level functional testing from UML specifications in end-of-production industrial environments. STTT 7(4): 326-340 (2005) |
| c91 | | Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: March AB, March AB1: new March tests for unlinked dynamic memory faults. ITC 2005: 8 |
| c90 | | Alfredo Benso, Alessandro Cilardo, Nicola Mazzocca, Liviu Miclea, Paolo Prinetto, Szilárd Enyedi: Reconfigurable systems self-healing using mobile hardware agents. ITC 2005: 9 |
| 2004 | ||
| j32 | | Paolo Prinetto, Alfredo Benso: Test Technology TC Newsletter. IEEE Design & Test of Computers 21(2): 164-165 (2004) |
| j31 | | Paolo Prinetto: Test Technology Technical Council Newsletter. J. Electronic Testing 20(2): 131-132 (2004) |
| j30 | | Paolo Prinetto: Test Technology Technical Council Newsletter. J. Electronic Testing 20(3): 221-225 (2004) |
| j29 | | Paolo Prinetto: Test Technology Technical Council Newsletter. J. Electronic Testing 20(4): 329 (2004) |
| j28 | | Paolo Prinetto: Test Technology Technical Council Newsletter. J. Electronic Testing 20(5): 461-462 (2004) |
| c89 | | Marie-Lise Flottes, Yves Bertrand, L. Balado, Emili Lupon, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, N. Pricopi, Hans-Joachim Wunderlich: Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ. DELTA 2004: 135-139 |
| c88 | | Liviu Miclea, Szilárd Enyedi, Gavril Toderean, Alfredo Benso, Paolo Prinetto: Towards Microagent based DBIST/DBISR. ITC 2004: 867-874 |
| 2003 | ||
| j27 | | Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: Online Self-Repair of FIR Filters. IEEE Design & Test of Computers 20(3): 50-57 (2003) |
| j26 | | Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian: A Hierarchical Infrastructure for SoC Test Management. IEEE Design & Test of Computers 20(4): 32-39 (2003) |
| j25 | | Andrea Baldini, Paolo Prinetto, Giovanni Denaro, Mauro Pezzè: Design for Testability for Highly Reconfigurable Component-Based Systems. Electr. Notes Theor. Comput. Sci. 82(6): 199-208 (2003) |
| c87 | | Fabrizio Bertuccelli, Franco Bigongiari, Andrea S. Brogna, Giorgio Di Natale, Paolo Prinetto, Roberto Saletti: Exhaustive Test of Several Dependable Memory Architectures Designed by GRAAL Tool. Asian Test Symposium 2003: 32-37 |
| c86 | | Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: A Watchdog Processor to Detect Data and Control Flow Errors. IOLTS 2003: 144-148 |
| c85 | | Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, I. Solcia, Luca Tagliaferri: FAUST: FAUlt-injection Script-based Tool. IOLTS 2003: 160 |
| c84 | | Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Luca Tagliaferri: Data Critically Estimation In Software Applications. ITC 2003: 802-810 |
| c83 | | Liviu Miclea, Szilárd Enyedi, Gavril Toderean, Alfredo Benso, Paolo Prinetto: Agent Based DBIST/DBISR And Its Web/Wireless Management. ITC 2003: 952-960 |
| c82 | | Yves Bertrand, Marie-Lise Flottes, L. Balado, Joan Figueras, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, N. Pricopi, Hans-Joachim Wunderlich, J.-P. Van der Heyden: Test Engineering Education in Europe: the EuNICE-Test Project. MSE 2003: 85-86 |
| c81 | | Andrea S. Brogna, Franco Bigongiari, Silvia Chiusano, Paolo Prinetto, Roberto Saletti: Designing and Testing High Dependable Memories for Aerospace Applications. VLSI-SOC 2003: 221- |
| 2002 | ||
| j24 | | Alfredo Benso, Silvia Chiusano, Paolo Prinetto: DFT and BIST of a Multichip Module for High-Energy Physics Experiments. IEEE Design & Test of Computers 19(3): 94-105 (2002) |
| j23 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero: Initializability analysis of synchronous sequential circuits. ACM Trans. Design Autom. Electr. Syst. 7(2): 249-264 (2002) |
| j22 | | Alfredo Benso, Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto: An on-line BIST RAM architecture with self-repair capabilities. IEEE Transactions on Reliability 51(1): 123-128 (2002) |
| c80 | | Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: Specification and Design of a New Memory Fault Simulator. Asian Test Symposium 2002: 92-97 |
| c79 | | Andrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei: Beyond UML to an End-of-Line Functional Test Engine. DATE 2002: 499-503 |
| c78 | | Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: An Optimal Algorithm for the Automatic Generation of March Tests. DATE 2002: 938-943 |
| c77 | | Michel Renovell, Penelope Faure, Paolo Prinetto, Yervant Zorian: Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA. DELTA 2002: 297-301 |
| c76 | | Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto: Automated Synthesis of SEU Tolerant Architectures from OO Descriptions. IOLTW 2002: 26-31 |
| c75 | | Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: Static Analysis of SEU Effects on Software Applications. ITC 2002: 500-508 |
| c74 | | Andrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei: Efficient Design of System Test: A Layered Architecture. ITC 2002: 930-939 |
| 2001 | ||
| j21 | | Alfredo Benso, Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni: Online and Offline BIST in IP-Core Design. IEEE Design & Test of Computers 18(5): 92-99 (2001) |
| j20 | | |
| j19 | | Alfredo Benso, Silvia Chiusano, Paolo Prinetto: A Self-Repairing Execution Unit for Microprogrammed Processors. IEEE Micro 21(5): 16-22 (2001) |
| c73 | | Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: Memory Read Faults: Taxonomy and Automatic Test Generation. Asian Test Symposium 2001: 157-163 |
| c72 | | Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Luca Tagliaferri: Control-Flow Checking via Regular Expressions. Asian Test Symposium 2001: 299-303 |
| c71 | | Yervant Zorian, Paolo Prinetto, João Paulo Teixeira, Isabel C. Teixeira, Carlos Eduardo Pereira, Octávio Páscoa Dias, Jorge Semião, Peter Muhmenthaler, W. Radermacher: Embedded tutorial: TRP: integrating embedded test and ATE. DATE 2001: 34-37 |
| c70 | | Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Hans-Joachim Wunderlich: On applying the set covering model to reseeding. DATE 2001: 156-161 |
| c69 | | Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: SEU effect analysis in an open-source router via a distributed fault injection environment. DATE 2001: 219-225 |
| c68 | | Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Luca Tagliaferri, Paolo Prinetto: Validation of a Software Dependability Tool via Fault Injection Experiments. IOLTW 2001: 3-8 |
| c67 | | Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Franco Bigongiari: GRAAL: a tool for highly dependable SRAMs generation. ITC 2001: 250-257 |
| c66 | | Andrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei: Towards a unified test process: from UML to end-of-line functional test. ITC 2001: 600-608 |
| 2000 | ||
| j18 | | Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian: A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures. J. Electronic Testing 16(3): 179-184 (2000) |
| c65 | | Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich: Optimal Hardware Pattern Generation for Functional BIST. DATE 2000: 292-297 |
| c64 | | Alfredo Benso, Silvia Chiusano, Paolo Prinetto, P. Simonotti, G. Ugo: Self-Repairing in a Micro-Programmed Processor for Dependable Applications. DFT 2000: 231-239 |
| c63 | | Andrea Baldini, Alfredo Benso, Silvia Chiusano, Paolo Prinetto: 'BOND': An Interposition Agents Based Fault Injector for Windows NT. DFT 2000: 387-395 |
| c62 | | Alfredo Benso, Silvia Chiusano, Paolo Prinetto, Luca Tagliaferri: A C/C++ Source-to-Source Compiler for Dependable Applications. DSN 2000: 71-78 |
| c61 | | Alfredo Benso, Stefano Martinetto, Paolo Prinetto, Riccardo Mariani: An SEU Injection Tool to Evaluate DSP-Based Architectures for Space Applications. ICCD 2000: 537-538 |
| c60 | | Alfredo Benso, Stefano Di Carlo, Silvia Chiusano, Paolo Prinetto, Fabio Ricciato, Monica Lobetti Bodoni, Maurizio Spadari: On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs. ICCD 2000: 539-540 |
| c59 | | Alfredo Benso, Silvia Chiusano, Paolo Prinetto: A COTS Wrapping Toolkit for Fault Tolerant Applications under Windows NT. IOLTW 2000: 9-16 |
| c58 | | Alfredo Benso, Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni: A Family of Self-Repair SRAM Cores. IOLTW 2000: 214-218 |
| c57 | | Alfredo Benso, Silvia Chiusano, Paolo Prinetto: A software development kit for dependable applications in embedded systems. ITC 2000: 170-178 |
| c56 | | Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni: A programmable BIST architecture for clusters of multiple-port SRAMs. ITC 2000: 557-566 |
| c55 | | Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich: Non-intrusive BIST for systems-on-a-chip. ITC 2000: 644-651 |
| c54 | | Alfredo Benso, Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Fabio Ricciato, Maurizio Spadari, Yervant Zorian: HD/sup 2/BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs. ITC 2000: 892-901 |
| 1999 | ||
| j17 | | Silvia Chiusano, Fulvio Corno, Paolo Prinetto: Exploiting Behavioral Information in Gate-Level ATPG. J. Electronic Testing 14(1-2): 141-148 (1999) |
| j16 | | Fulvio Corno, Uwe Gläser, Paolo Prinetto, Matteo Sonza Reorda, Heinrich Theodor Vierhaus, Massimo Violante: SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information. IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 191-202 (1999) |
| c53 | | Alfredo Benso, Silvia Chiusano, Paolo Prinetto, Simone Giovannetti, Riccardo Mariani, Silvano Motto: Testing an MCM for high-energy physics experiments: a case study. ITC 1999: 38-46 |
| c52 | | Monica Lobetti Bodoni, Alessio Pricco, Alfredo Benso, Silvia Chiusano, Paolo Prinetto: An on-line BISTed SRAM IP core. ITC 1999: 993-1000 |
| c51 | | Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian: HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs. ITC 1999: 1038-1044 |
| c50 | | Silvia Chiusano, Fulvio Corno, Paolo Prinetto: RT-level TPG Exploiting High-Level Synthesis Information. VTS 1999: 341-353 |
| 1998 | ||
| j15 | | Stefano Barbagallo, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda: Integrating Online and Offline Testing of a Switching Memory. IEEE Design & Test of Computers 15(1): 63-70 (1998) |
| j14 | | Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda: The General Product Machine: a New Model for Symbolic FSM Traversal. Formal Methods in System Design 12(3): 267-289 (1998) |
| j13 | | Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: EXFI: a low-cost fault injection system for embedded microprocessor-based boards. ACM Trans. Design Autom. Electr. Syst. 3(4): 626-634 (1998) |
| c49 | | Silvia Chiusano, Fulvio Corno, Paolo Prinetto: A Test Pattern Generation Algorithm Exploiting Behavioral Information. Asian Test Symposium 1998: 480-485 |
| c48 | | Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda: Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques. DATE 1998: 570-576 |
| c47 | | Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante: Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection. DATE 1998: 670-677 |
| c46 | | Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: A fault injection environment for microprocessor-based boards. ITC 1998: 768-773 |
| c45 | | Fulvio Corno, Nicola Gaudenzi, Paolo Prinetto, Matteo Sonza Reorda: On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits. VTS 1998: 424-429 |
| c44 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: A Test Pattern Generation Methodology for Low-Power Consumption. VTS 1998: 453-459 |
| 1997 | ||
| c43 | | Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: Guaranteeing Testability in Re-encoding for Low Power. Asian Test Symposium 1997: 30-35 |
| c42 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero: A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits. Asian Test Symposium 1997: 56-61 |
| c41 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG. Asian Test Symposium 1997: 68-73 |
| c40 | | Mario Baldi, Fulvio Corno, Maurizio Rebaudengo, Paolo Prinetto, Matteo Sonza Reorda, Giovanni Squillero: Simulation-based verification of network protocols performance. CHARME 1997: 236-251 |
| c39 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: New static compaction techniques of test sequences for sequential circuits. ED&TC 1997: 37-43 |
| c38 | | Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda: Hybrid symbolic-explicit techniques for the graph coloring problem. ED&TC 1997: 422-426 |
| c37 | | Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Raimund Ubar: A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs. ED&TC 1997: 560-565 |
| c36 | | Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar: Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. DFT 1997: 212-217 |
| c35 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero: A new Approach for Initialization Sequences Computation for Synchronous Sequential Circuits. ICCD 1997: 381-386 |
| c34 | | S. Chuisano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization. ICTAI 1997: 133- |
| c33 | | Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda: Testability Analysis and ATPG on Behavioral RT-Level VHDL. ITC 1997: 753-759 |
| c32 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: SAARA: a simulated annealing algorithm for test pattern generation for digital circuits. SAC 1997: 228-232 |
| c31 | | Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda: Cellular automata for deterministic sequential test pattern generation. VTS 1997: 60-67 |
| c30 | | J. Abraham, P. Frankl, Christian Landrault, Meryem Marzouki, Paolo Prinetto, Chantal Robach, Pascale Thévenod-Fosse: Hardware Test: Can We Learn from Software Testing? VTS 1997: 320-321 |
| 1996 | ||
| j12 | | Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda: Circular Self-Test Path for FSMs. IEEE Design & Test of Computers 13(4): 50-60 (1996) |
| j11 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 15(8): 991-1000 (1996) |
| c29 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Maurizio Damiani, Leonardo Impagliazzo, G. Sartore: On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications. EDCC 1996: 190-202 |
| c28 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits. HPCN Europe 1996: 454-459 |
| c27 | | Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda: A Genetic Algorithm for Automatic Generation of Test Logic for Digital Circuits. ICTAI 1996: 10-16 |
| c26 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: Comparing Topological, Symbolic and GA-based ATPGs: An Experimental Approach. ITC 1996: 39-47 |
| c25 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs. ITC 1996: 558-564 |
| c24 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Cicuits. PPSN 1996: 792-800 |
| c23 | | Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda: Scan insertion criteria for low design impact. VTS 1996: 26-31 |
| 1995 | ||
| j10 | | Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda, Stefano Barbagallo, Andrea Burri, Davide Medina: Industrial BIST of Embedded RAMs. IEEE Design & Test of Computers 12(3): 86-95 (1995) |
| c22 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva: A PVM tool for automatic test generation on parallel and distributed systems. HPCN Europe 1995: 39-44 |
| c21 | | Stefano Barbagallo, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda: Testing a Switching Memory in a Telcommunication System. ITC 1995: 947-956 |
| c20 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva: A portable ATPG tool for parallel and distributed systems. VTS 1995: 29-34 |
| c19 | | Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Uwe Gläser, Heinrich Theodor Vierhaus: Improving topological ATPG with symbolic techniques. VTS 1995: 338-343 |
| 1994 | ||
| c18 | | Paolo Prinetto, Fulvio Corno, Matteo Sonza Reorda: An experimental analysis of the effectiveness of the circular self-test path technique. EURO-DAC 1994: 246-251 |
| c17 | | Catherine Bayol, Bernard Soulas, Dominique Borrione, Fulvio Corno, Paolo Prinetto: A process algebra interpretation of a verification oriented overlanguage of VHDL. EURO-DAC 1994: 506-511 |
| c16 | | Paolo Camurati, Fulvio Corno, Paolo Prinetto, Catherine Bayol, Bernard Soulas: System-Level Modeling and Verification: a Comprehensive Design Methodology. EDAC-ETC-EUROASIC 1994: 636-640 |
| c15 | | Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva: GATTO: An Intelligent Tool for Automatic Test Pattern Generation for Digital Circuits. ICTAI 1994: 411-417 |
| c14 | | Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms. ITC 1994: 240-249 |
| c13 | | Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda: Making the Circular Self-Test Path Technique Effective for Real Circuits. ITC 1994: 949-957 |
| c12 | | Paolo Camurati, Fulvio Corno, Michela Meo, Paolo Prinetto: A new functional fault model for system-level descriptions. VTS 1994: 214-219 |
| c11 | | Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda, Stefano Barbagallo, Andrea Burri, Davide Medina: An industrial experience in the built-in self test of embedded RAMs. VTS 1994: 306-311 |
| 1993 | ||
| j9 | | Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda: An approach to sequential circuit diagnosis based on formal verification techniques. J. Electronic Testing 4(1): 11-17 (1993) |
| c10 | | Paolo Camurati, Fulvio Corno, Paolo Prinetto: A Methodology for System-Level Design for Verifiability. CHARME 1993: 80-91 |
| c9 | | Paolo Camurati, Fulvio Corno, Paolo Prinetto: Exploiting Symbolic Traversal Techniques for Efficient Process Algebra Manipulation. CHDL 1993: 31-44 |
| 1992 | ||
| c8 | | Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Silvano Gai, Paolo Prinetto, Matteo Sonza Reorda: A New Model for Improving symbolic Product Machine Traversal. DAC 1992: 614-619 |
| c7 | | Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda: Sequential Circuit Diagnosis Based on Formal Verification Techniques. ITC 1992: 187-196 |
| 1991 | ||
| j8 | | Gianpiero Cabodi, Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda: TPDL: Extended Temporal Profile Description Language. Softw., Pract. Exper. 21(4): 355-374 (1991) |
| 1990 | ||
| j7 | | Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda: Exact probabilistic testability measures for multi-output circuits. J. Electronic Testing 1(3): 229-234 (1990) |
| c6 | | Paolo Camurati, M. Gilli, Paolo Prinetto, Matteo Sonza Reorda: The Use of Model Checking in ATPG for Sequential Circuits. CAV 1990: 86-95 |
| c5 | | Paolo Camurati, Antonio Lioy, Paolo Prinetto, Matteo Sonza Reorda: Diagnosis oriented test pattern generation. EURO-DAC 1990: 470-474 |
| c4 | | Paolo Camurati, Davide Medina, Paolo Prinetto, Matteo Sonza Reorda: A diagnostic test pattern generation algorithm. ITC 1990: 52-58 |
| 1989 | ||
| c3 | | Dominique Borrione, Paolo Prinetto: Zero-Defect Designs, Why and How: Formal Verification vs. Automated Synthesis. IFIP Congress 1989: 233-240 |
| 1988 | ||
| j6 | | Paolo Camurati, Paolo Prinetto: Formal Verification of Hardware Correctness: Introduction and Survey of Current Research. IEEE Computer 21(7): 8-19 (1988) |
| j5 | | Paolo Camurati, P. Gianoglio, R. Gianoglio, Paolo Prinetto: ESTA: an expert system for DFT rule verification. IEEE Trans. on CAD of Integrated Circuits and Systems 7(11): 1172-1180 (1988) |
| 1986 | ||
| c2 | | Gianpiero Cabodi, Paolo Camurati, Paolo Prinetto: Experiences in Prolog-Based DFT Rule Checking. FJCC 1986: 909-914 |
| 1985 | ||
| j4 | | Fabio Somenzi, Silvano Gai, Marco Mezzalama, Paolo Prinetto: Testing Strategy and Technique for Macro-Based Circuits. IEEE Trans. Computers 34(1): 85-90 (1985) |
| 1984 | ||
| j3 | | Fabio Somenzi, Silvano Gai, Marco Mezzalama, Paolo Prinetto: PART: Programmable Array Testing Based on a Partitioning Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 3(2): 142-149 (1984) |
| 1983 | ||
| j2 | | Marco Mezzalama, Paolo Prinetto: A Hierarchical Description Model for Microcode. IEEE Trans. Computers 32(5): 478-487 (1983) |
| c1 | | Fabio Somenzi, Silvano Gai, Marco Mezzalama, Paolo Prinetto: A new integrated system for PLA testing and verification. DAC 1983: 57-63 |
| 1982 | ||
| j1 | | Marco Mezzalama, Paolo Prinetto: A Machine-independent Approach to Microprogram Synthesis. Softw., Pract. Exper. 12(10): 985-1010 (1982) |
Colors in the list of coauthors
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