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Stylianos D. Pezaris

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1980 – 1989

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1989
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Stylianos D. Pezaris:
Shift-reduce conflicts in LR parsers. ACM SIGPLAN Notices 24(11): 94-95 (1989)

1970 – 1979

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1971
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Stylianos D. Pezaris:
A 40-ns 17-Bit by 17-Bit Array Multiplier. IEEE Trans. Computers 20(4): 442-447 (1971)

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