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Gerald G. Pechanek
2000 – 2009
- 2003
[j3]Nikos Pitsianis, Gerald G. Pechanek: Indirect VLIW memory allocation for the ManArray multiprocessor DSP. SIGARCH Computer Architecture News 31(1): 69-74 (2003)- 2000
- [j2]Koen Bertels, Luc Neuberg, Stamatis Vassiliadis, Gerald G. Pechanek: A look inside the learning process of neural networks. Complexity 5(6): 34-38 (2000)
- [c7]Gerald G. Pechanek, Stamatis Vassiliadis: The ManArray( Embedded Processor Architecture. EUROMICRO 2000: 1348-1355
- [c6]Bruce Schulman, Gerald G. Pechanek: A 90k Gate ``CLB'' for Parallel Distributed Computing. IPDPS Workshops 2000: 831-838
1990 – 1999
- 1999
- [j1]Valentine C. Aikens II, José G. Delgado-Frias, Gerald G. Pechanek, Stamatis Vassiliadis: A neuro-emulator with embedded capabilities for generalized learning. Journal of Systems Architecture 45(14): 1219-1243 (1999)
- [c5]Gerald G. Pechanek, Stamatis Vassiliadis, Nikos Pitsianis: ManArray Processor Interconnection Network: An Introduction. Euro-Par 1999: 761-765
- 1998
- [c4]Stamatis Vassiliadis, Edwin A. Hakkennes, J. S. S. M. Wong, Gerald G. Pechanek: The Sum-Absolute-Difference Motion Estimation Accelerato. EUROMICRO 1998: 20559-20566
- 1996
- [c3]Chris H. L. Moller, Gerald G. Pechanek: Architectural simulation system for M.f.a.s.t. Annual Simulation Symposium 1996: 221-
- 1995
- [c2]Gerald G. Pechanek, M. Stojancic, Stamatis Vassiliadis, C. John Glossner: MFAST: a single chip highly parallel image processing architecture. ICIP 1995: 69-72
- [c1]Valentine C. Aikens II, Steven M. Barber, José G. Delgado-Frias, Gerald G. Pechanek, Stamatis Vassiliadis: A Neuro-Architecture with Embedded Learning. Parallel and Distributed Computing and Systems 1995: 103-106
Coauthor Index
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last updated on 2013-04-29 01:09 CEST by the dblp team