Sanjay J. Patel

John H. Kelm, Daniel R. Johnson, William Tuohy, Steven S. Lumetta, Sanjay J. Patel: Cohesion: An Adaptive Hybrid Memory Model for Accelerators. IEEE Micro 31(1): 42-55 (2011)

Daniel R. Johnson, Matthew R. Johnson, John H. Kelm, William Tuohy, Steven S. Lumetta, Sanjay J. Patel: Rigel: A 1, 024-Core Single-Chip Accelerator Architecture. IEEE Micro 31(4): 30-41 (2011)

Minh N. Do, Quang H. Nguyen, Ha T. Nguyen, Daniel Kubacki, Sanjay J. Patel: Immersive Visual Communication. IEEE Signal Process. Mag. 28(1): 58-66 (2011)

Neal Clayton Crago, Sanjay J. Patel: Decoupled Architectures as a Low-Complexity Alternative to Out-of-order Execution. PACT 2011: 179-180

Hongbo Zhang, Tan Yan, Martin D. F. Wong, Sanjay J. Patel: Accelerating aerial image simulation with GPU. ICCAD 2011: 178-184

Neal Clayton Crago, Sanjay J. Patel: OUTRIDER: efficient memory latency tolerance with decoupled strands. ISCA 2011: 117-128

John H. Kelm, Daniel R. Johnson, Steven S. Lumetta, Sanjay J. Patel, Matthew I. Frank: A Task-Centric Memory Model for Scalable Accelerator Architectures. IEEE Micro 30(1): 29-39 (2010)

John H. Kelm, Matthew R. Johnson, Steven S. Lumetta, Sanjay J. Patel: WAYPOINT: scaling coherence to thousand-core architectures. PACT 2010: 99-110

Isaac Gelado, Javier Cabezas, Nacho Navarro, John E. Stone, Sanjay J. Patel, Wen-mei W. Hwu: An asymmetric distributed shared memory model for heterogeneous parallel systems. ASPLOS 2010: 347-358

Omid Azizi, Aqeel Mahesri, John P. Stevenson, Sanjay J. Patel, Mark Horowitz: An integrated framework for joint design space exploration of microarchitecture and circuits. DATE 2010: 250-255

Shobha Vasudevan, David Sheridan, Sanjay J. Patel, David Tcheng, William Tuohy, Daniel R. Johnson: GoldMine: Automatic assertion generation using data mining and static analysis. DATE 2010: 626-629

Omid Azizi, Aqeel Mahesri, Benjamin C. Lee, Sanjay J. Patel, Mark Horowitz: Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis. ISCA 2010: 26-36

Stephen M. Kofsky, Daniel R. Johnson, John A. Stratton, Wen-mei W. Hwu, Sanjay J. Patel, Steven S. Lumetta: Implementing a GPU Programming Model on a Non-GPU Accelerator Architecture. ISCA Workshops 2010: 40-51

John H. Kelm, Daniel R. Johnson, William Tuohy, Steven S. Lumetta, Sanjay J. Patel: Cohesion: a hybrid memory model for accelerators. ISCA 2010: 429-440

Sara S. Baghsorkhi, Matthieu Delahaye, Sanjay J. Patel, William D. Gropp, Wen-mei W. Hwu: An adaptive performance modeling tool for GPU architectures. PPOPP 2010: 105-114

Omid Azizi, Aqeel Mahesri, Sanjay J. Patel, Mark Horowitz: Area-efficiency in CMP core design: co-optimization of microarchitecture and physical design. SIGARCH Computer Architecture News 37(2): 56-65 (2009)

Thomas Y. Yeh, Glenn Reinman, Sanjay J. Patel, Petros Faloutsos: Fool me twice: Exploring and exploiting error tolerance in physics-based animation. ACM Trans. Graph. 29(1) (2009)

John H. Kelm, Daniel R. Johnson, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel: A Task-Centric Memory Model for Scalable Accelerator Architectures. PACT 2009: 77-87

Albert Sidelnik, I-Jui Sung, Wanmin Wu, María Jesús Garzarán, Wen-mei W. Hwu, Klara Nahrstedt, David A. Padua, Sanjay J. Patel: Optimization of tele-immersion codes. GPGPU 2009: 85-93

Quang H. Nguyen, Minh N. Do, Sanjay J. Patel: Depth image-based rendering with low resolution depth. ICIP 2009: 553-556

John H. Kelm, Daniel R. Johnson, Matthew R. Johnson, Neal Clayton Crago, William Tuohy, Aqeel Mahesri, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel: Rigel: an architecture and scalable programming interface for a 1000-core accelerator. ISCA 2009: 140-151

Sanjay J. Patel, Wen-mei W. Hwu: Guest Editors' Introduction: Accelerator Architectures. IEEE Micro 28(4): 4-12 (2008)

Aqeel Mahesri, Daniel R. Johnson, Neal Clayton Crago, Sanjay J. Patel: Tradeoffs in designing accelerator architectures for visual computing. MICRO 2008: 164-175

Aqeel Mahesri, Nicholas J. Wang, Sanjay J. Patel: Hardware support for software controlled multithreading. SIGARCH Computer Architecture News 35(1): 3-12 (2007)

Wen-mei W. Hwu, Shane Ryoo, Sain-Zee Ueng, John H. Kelm, Isaac Gelado, Sam S. Stone, Robert E. Kidd, Sara S. Baghsorkhi, Aqeel Mahesri, Stephanie C. Tsao, Nacho Navarro, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel: Implicitly Parallel Programming Models for Thousand-Core Microprocessors. DAC 2007: 754-759

Thomas Y. Yeh, Petros Faloutsos, Sanjay J. Patel, Glenn Reinman: ParallAX: an architecture for real-time physics. ISCA 2007: 232-243

Nicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel: Examining ACE analysis reliability estimates using fault-injection. ISCA 2007: 460-469

Thomas Y. Yeh, Petros Faloutsos, Milos Ercegovac, Sanjay J. Patel, Glenn Reinman: The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration. MICRO 2007: 394-406

Ronald D. Barnes, John W. Sias, Erik M. Nystrom, Sanjay J. Patel, Jose (Nacho) Navarro, Wen-mei W. Hwu: Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining. IEEE Trans. Computers 55(1): 18-33 (2006)

Nicholas J. Wang, Sanjay J. Patel: ReStore: Symptom-Based Soft Error Detection in Microprocessors. IEEE Trans. Dependable Sec. Comput. 3(3): 188-201 (2006)

Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, Nicholas J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, Sanjay J. Patel: Sequential Element Design With Built-In Soft Error Resilience. IEEE Trans. VLSI Syst. 14(12): 1368-1378 (2006)

Giacinto Paolo Saggese, Nicholas J. Wang, Zbigniew Kalbarczyk, Sanjay J. Patel, Ravishankar K. Iyer: An Experimental Study of Soft Errors in Microprocessors. IEEE Micro 25(6): 30-39 (2005)

Nicholas J. Wang, Sanjay J. Patel: ReStore: Symptom Based Soft Error Detection in Microprocessors. DSN 2005: 30-39

Wen-mei W. Hwu, Sanjay J. Patel: The Future of Computer Architecture Research: An Industrial Perspective. HPCA 2005: 264

Brian Fahs, Todd M. Rafacz, Sanjay J. Patel, Steven S. Lumetta: Continuous Optimization. ISCA 2005: 86-97

Yale N. Patt, Sanjay J. Patel: Introduction to computing systems - from bits and gates to C and beyond (2. ed.). McGraw-Hill 2004, isbn 978-0-07-246750-5, pp. I-XXIV, 1-632

Nicholas J. Wang, Justin Quek, Todd M. Rafacz, Sanjay J. Patel: Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline. DSN 2004: 61-

Todd E. Ehrhart, Sanjay J. Patel: Reducing the Scheduling Critical Cycle Using Wakeup Prediction. HPCA 2004: 222-231

Nicholas J. Wang, Michael Fertig, Sanjay J. Patel: Y-Branches: When You Come to a Fork in the Road, Take It. IEEE PACT 2003: 56-66

Francesco Spadini, Brian Fahs, Sanjay J. Patel, Steven S. Lumetta: Improving Quasi-Dynamic Schedules through Region Slip. CGO 2003: 149-158

Brian Slechta, David Crowe, Brian Fahs, Michael Fertig, Gregory A. Muthler, Justin Quek, Francesco Spadini, Sanjay J. Patel, Steven Lumetta: Dynamic Optimization of Micro-Operations. HPCA 2003: 165-176

Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu: Beating in-order stalls with "flea-flicker" two-pass pipelining. MICRO 2003: 387-398

Steven Lumetta, Sanjay J. Patel: Characterization of essential dynamic instructions. SIGMETRICS 2003: 308-309

Gregory A. Muthler, David Crowe, Sanjay J. Patel, Steven Lumetta: Instruction fetch deferral using static slack. MICRO 2002: 51-61

Sanjay J. Patel, Steven Lumetta: rePLay: A Hardware Framework for Dynamic Optimization. IEEE Trans. Computers 50(6): 590-608 (2001)

Brian Fahs, Satarupa Bose, Matthew M. Crum, Brian Slechta, Francesco Spadini, Tony Tung, Sanjay J. Patel, Steven S. Lumetta: Performance characterization of a hardware mechanism for dynamic optimization. MICRO 2001: 16-27

Sanjay J. Patel, Tony Tung, Satarupa Bose, Matthew M. Crum: Increasing the size of atomic instruction blocks using control flow assertions. MICRO 2000: 303-313

Sanjay J. Patel, Daniel H. Friendly, Yale N. Patt: Evaluation of Design Options for the Trace Cache Fetch Mechanism. IEEE Trans. Computers 48(2): 193-204 (1999)

Marius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt: An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work. ISCA 1998: 52-61

Sanjay J. Patel, Marius Evers, Yale N. Patt: Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. ISCA 1998: 262-271

Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt: Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors. MICRO 1998: 173-181

Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, Jared Stark: One Billion Transistors, One Uniprocessor, One Chip. IEEE Computer 30(9): 51-57 (1997)

Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt: Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism. MICRO 1997: 24-33

Dina L. McKinney, Masooma Bhaiwala, Kwong-Tak A. Chui, Christopher L. Houghton, James R. Mullens, Daniel L. Leibholz, Sanjay J. Patel, Delvan A. Ramey, Mark B. Rosenbluth: Digital's DECchip 21066: The First Cost-focused Alpha AXP Chip. Digital Technical Journal 6(1) (1994)

Dina L. McKinney, Daniel L. Leibholz, Mark B. Rosenbluth, James R. Mullens, Kwong-Tak A. Chui, Masooma Bhaiwala, Sanjay J. Patel, Christopher L. Houghton, Delvan A. Ramey: DECchip 21066: The Alpha AXP Chip for Cost-Focused Systems. COMPCON 1994: 406-413

Sanjay J. Patel, Janak H. Patel: Effectiveness of heuristics measures for automatic test pattern generation. DAC 1986: 547-552