Rubin A. Parekhji

Rajesh Mittal, Lakshmanan Balasubramanian, Y. B. Chethan Kumar, V. R. Devanathan, Mudasir Kawoosa, Rubin A. Parekhji: Towards adaptive test of multi-core RF SoCs. DATE 2013: 743-748

Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji: Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands. IEEE Trans. on CAD of Integrated Circuits and Systems 31(11): 1754-1766 (2012)

Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji: Time-division multiplexing for testing SoCs with DVS and multiple voltage islands. European Test Symposium 2012: 1-6

V. Prasanth, Virendra Singh, Rubin A. Parekhji: Derating based hardware optimizations in soft error tolerant designs. VTS 2012: 282-287

Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi: Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test. J. Low Power Electronics 7(4): 502-515 (2011)

Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji: Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands. Asian Test Symposium 2011: 33-39

V. Prasanth, Virendra Singh, Rubin A. Parekhji: Reduced overhead soft error mitigation using error control coding techniques. IOLTS 2011: 163-168

Rajesh Mittal, Lakshmanan Balasubramanian, Adesh Sontakke, Harikrishna Parthasarathy, Prakash Narayanan, Puneet Sabbarwal, Rubin A. Parekhji: DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management. ITC 2011: 1-10

Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi: Multi-CoDec Configurations for Low Power and High Quality Scan Test. VLSI Design 2011: 370-375

Srinivasulu Alampally, R. T. Venkatesh, P. Shanmugasundaram, Rubin A. Parekhji, V. D. Agrawal: An efficient test data reduction technique through dynamic pattern mixing across multiple fault models. VTS 2011: 285-290

M. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji: False Error Vulnerability Study of On-line Soft Error Detection Mechanisms. J. Electronic Testing 26(3): 323-335 (2010)

V. Prasanth, Virendra Singh, Rubin A. Parekhji: Robust detection of soft errors using delayed capture methodology. IOLTS 2010: 277-282

Rubin A. Parekhji: Innovative practices session 1C: Innovative practices in RF test. VTS 2010: 39

Rajesh Mittal, Adesh Sontakke, Rubin A. Parekhji: Test time reduction using parallel RF test techniques. VTS 2010: 40

Amit Sabne, Rajesh Tiwari, Abhijeet Shrivastava, Srivaths Ravi, Rubin A. Parekhji: A generic low power scan chain wrapper for designs using scan compression. VTS 2010: 135-140

Hongxia Fang, Krishnendu Chakrabarty, Rubin A. Parekhji: Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect Coverage. Asian Test Symposium 2009: 331-336

Amit Dutta, Malav Shah, G. Swathi, Rubin A. Parekhji: Design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-test. IOLTS 2009: 237-242

Srivaths Ravi, Rubin A. Parekhji, Jayashree Saxena: Low Power Test for Nanometer System-on-Chips (SoCs). J. Low Power Electronics 4(1): 81-100 (2008)

M. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji: False Error Study of On-line Soft Error Detection Mechanisms. IOLTS 2008: 53-58

Amit Dutta, Srinivasulu Alampally, V. Prasanth, Rubin A. Parekhji: DFT Implementationis for Striking the Right Balance between Test Cost and Test Quality for Automotive SOCs. ITC 2008: 1-10

Sudhakar Surendran, Rubin A. Parekhji, R. Govindarajan: A systematic approach to synthesis of verification test-suites for modular SoC designs. SoCC 2008: 91-96

Rajesh Tiwari, Abhijeet Shrivastava, Mahit Warhadpande, Srivaths Ravi, Rubin A. Parekhji: A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips. VTS 2008: 53-58

Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji: Methodology for low power test pattern generation using activity threshold control logic. ICCAD 2007: 526-529

Sandeep Jain, Jais Abraham, Srinivas Kumar Vooka, Sumant Kale, Amit Dutta, Rubin A. Parekhji: Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs. VLSI Design 2007: 339-344

Subir K. Roy, Rubin A. Parekhji: Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs. VLSI Design 2007: 364-372

Satish Yada, Bharadwaj S. Amrutur, Rubin A. Parekhji: Modified Stability Checking for On-line Error Detection. VLSI Design 2007: 787-792

Sanjay K. Thakur, Rubin A. Parekhji, Arun N. Chandorkar: On-chip Test and Repair of Memories for Static and Dynamic Faults. ITC 2006: 1-10

Rubin A. Parekhji: Session Abstract. VTS 2006: 86-87

Sameer Goel, Rubin A. Parekhji: Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency. Asian Test Symposium 2005: 330-336

Rubin A. Parekhji: DFT for Low Cost SOC Test. Asian Test Symposium 2005: 451

Carol Stolicny, Tapio Koivukangas, Rubin A. Parekhji, Ian G. Harris, Rob Aitken: ITC 2003 panels: Part 1. IEEE Design & Test of Computers 21(2): 160-163 (2004)

Ambar A. Gadkari, S. Ramesh, Rubin A. Parekhji: CESC: a visual formalism for specification and verification of SoCs. ACM Great Lakes Symposium on VLSI 2004: 354-357

K. Nikila, Rubin A. Parekhji: DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI's TNETD7300 ADSL Modem Device. ITC 2004: 773-782

Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji, Arun N. Chandorkar: Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories. VLSI Design 2004: 753-756

Rubin A. Parekhji: Panel Synopsis - How (In)Adequate is One Time Testing? ITC 2003: 1279

Rubin A. Parekhji: Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions. VLSI Design 2003: 17

Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji: Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. VLSI Design 2002: 781-788

Ameet Bagwe, Rubin A. Parekhji: Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems. Asian Test Symposium 2000: 260-

Jais Abraham, Narayan Prasad, Srinivasa Chakravarthy B. S., Ameet Bagwe, Rubin A. Parekhji: A framework to evaluate test tradeoffs in embedded core based systems-case study on TI's TMS320C27xx. ITC 2000: 417-425

Rubin A. Parekhji: Test Techniques and Trade-offs for Embedded Cores and Systems. VLSI Design 2000: 5

Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar: Monitoring machine based synthesis technique for concurrent error detection in finite state machines. J. Electronic Testing 8(2): 179-201 (1996)

Michael Nicolaidis, Rubin A. Parekhji, M. Boudjit: E-Groups: A New Technique for Fast Backward Propagation in System Level Test Generation. Asian Test Symposium 1996: 34-41

Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar: Concurrent Error Detection Using Monitoring Machines. IEEE Design & Test of Computers 12(3): 24-32 (1995)

B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh: A new methodology for the design of low-cost fail safe circuits and networks. VLSI Design 1995: 355-358

Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar: State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits. VLSI Design 1993: 15-20

Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar: A Methodology for Designing Optimal Self-Checking Sequential Circuits. ITC 1991: 283-291

Rubin A. Parekhji, N. K. Nanda: Design methodology and microdiagnostics development for a self-checking microprocessor. MICRO 1989: 70-82