Marios C. Papaefthymiou

Visvesh S. Sathe, Srikanth Arekapudi, Alexander T. Ishii, Charles Ouyang, Marios C. Papaefthymiou, Samuel Naffziger: Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor. J. Solid-State Circuits 48(1): 140-149 (2013)

Arun Raghavan, Laurel Emurian, Lei Shao, Marios C. Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch, Milo M. K. Martin: Computational sprinting on a hardware/software testbed. ASPLOS 2013: 155-166

Jerry C. Kao, Wei-Hsiang Ma, Visvesh S. Sathe, Marios C. Papaefthymiou: Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic. IEEE Trans. VLSI Syst. 20(6): 977-988 (2012)

Arun Raghavan, Yixin Luo, Anuj Chandawalla, Marios C. Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch, Milo M. K. Martin: Computational sprinting. HPCA 2012: 249-260

Visvesh S. Sathe, Srikanth Arekapudi, Charles Ouyang, Marios C. Papaefthymiou, Alexander T. Ishii, Samuel Naffziger: Resonant clock design for a power-efficient high-volume x86-64 microprocessor. ISSCC 2012: 68-70

Wei-Hsiang Ma, Jerry C. Kao, Marios C. Papaefthymiou: A 5.5GS/s 28mW 5-bit flash ADC with resonant clock distribution. ESSCIRC 2011: 155-158

Wei-Hsiang Ma, Jerry C. Kao, Visvesh S. Sathe, Marios C. Papaefthymiou: 187 MHz Subthreshold-Supply Charge-Recovery FIR. J. Solid-State Circuits 45(4): 793-803 (2010)

Zhengtao Yu, Marios C. Papaefthymiou, Xun Liu: Skew spreading for peak current reduction. ACM Great Lakes Symposium on VLSI 2007: 461-464

Xun Liu, Yuantao Peng, Marios C. Papaefthymiou: RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power. CoRR abs/0710.4690 (2007)

Xun Liu, Yuantao Peng, Marios C. Papaefthymiou: Practical repeater insertion for low power: what repeater library do we need? IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 917-924 (2006)

Jiyoun Kim, Marios C. Papaefthymiou, José Neves: Parallelizing post-placement timing optimization. IPDPS 2006

Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou: Charge-Recovery Computing on Silicon. IEEE Trans. Computers 54(6): 651-659 (2005)

Xun Liu, Marios C. Papaefthymiou: HyPE: hybrid power estimation for IP-based systems-on-chip. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1089-1103 (2005)

Visvesh S. Sathe, Juang-Ying Chueh, Joohee Kim, Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou: Fast, efficient, recovering, and irreversible. Conf. Computing Frontiers 2005: 407-413

Xun Liu, Yuantao Peng, Marios C. Papaefthymiou: RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power. DATE 2005: 1330-1335

Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler: A GHz-class charge recovery logic. ISLPED 2005: 91-94

Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler: Boost Logic: A High Speed Energy Recovery Circuit Family. ISVLSI 2005: 22-27

Juang-Ying Chueh, Marios C. Papaefthymiou, Conrad H. Ziesler: Two-Phase Resonant Clock Distribution. ISVLSI 2005: 65-70

Jiyoun Kim, José Neves, Marios C. Papaefthymiou: Multi-Session Partitioning for Parallel Timing Optimization. PDCAT 2005: 598-602

Xun Liu, Marios C. Papaefthymiou: A Markov chain sequence generator for power macromodeling. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1048-1062 (2004)

Xun Liu, Yuantao Peng, Marios C. Papaefthymiou: Practical repeater insertion for low power: what repeater library do we need? DAC 2004: 30-35

Jiyoun Kim, Marios C. Papaefthymiou, Athar B. Tayyab: An Algorithm for Geometric Load Balancing with Two Constraints. IPDPS 2004

Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou: Empirical evaluation of timing and power in resonant clock distribution. ISCAS (2) 2004: 249-252

Joohee Kim, Marios C. Papaefthymiou: Constant-load energy recovery memory for efficient high-speed operation. ISLPED 2004: 240-243

Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou: Experimental Evaluation of Resonant Clock Distribution. ISVLSI 2004: 135-140

Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman: Clock tree layout design for reduced delay uncertainty. SoCC 2004: 179-180

Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou: Fine-grain real-time reconfigurable pipelining. IBM Journal of Research and Development 47(5-6): 599-610 (2003)

Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou: A true single-phase energy-recovery multiplier. IEEE Trans. VLSI Syst. 11(2): 194-207 (2003)

Xun Liu, Marios C. Papaefthymiou: Design of a 20-mb/s 256-state Viterbi decoder. IEEE Trans. VLSI Syst. 11(6): 965-975 (2003)

Joohee Kim, Marios C. Papaefthymiou: Block-based multiperiod dynamic memory design for low data-retention power. IEEE Trans. VLSI Syst. 11(6): 1006-1018 (2003)

Xun Liu, Marios C. Papaefthymiou: HyPE: hybrid power estimation for IP-based programmable systems. ASP-DAC 2003: 606-609

Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman: Reduced Delay Uncertainty in High Performance Clock Distribution Networks. DATE 2003: 10068-10075

Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe, Marios C. Papaefthymiou: A 225 MHz resonant clocked ASIC chip. ISLPED 2003: 48-53

Conrad H. Ziesler, Joohee Kim, Marios C. Papaefthymiou: Energy Recovering ASIC Design. ISVLSI 2003: 133-138

Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman: Retiming and clock scheduling for digital circuit optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 184-203 (2002)

Xun Liu, Marios C. Papaefthymiou: Design of a high-throughput low-power IS95 Viterbi decoder. DAC 2002: 263-268

Xun Liu, Marios C. Papaefthymiou: A Markov chain sequence generator for power macromodeling. ICCAD 2002: 404-411

Xun Liu, Marios C. Papaefthymiou: Incorporation of input glitches into power macromodeling. ISCAS (4) 2002: 846-849

Joohee Kim, Conrad H. Ziesler, Marios C. Papaefthymiou: Energy recovering static memory. ISLPED 2002: 92-97

Farinaz Koushanfar, Darko Kirovski, Inki Hong, Miodrag Potkonjak, Marios C. Papaefthymiou: Symbolic debugging of embedded hardware and software. IEEE Trans. on CAD of Integrated Circuits and Systems 20(3): 392-401 (2001)

Suhwan Kim, Marios C. Papaefthymiou: True single-phase adiabatic circuitry. IEEE Trans. VLSI Syst. 9(1): 52-63 (2001)

Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou: Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier. ARVLSI 2001: 42-58

Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou: A True Single-Phase 8-bit Adiabatic Multiplier. DAC 2001: 758-763

Xun Liu, Marios C. Papaefthymiou: A static power estimation methodolodgy for IP-based design. DATE 2001: 280-289

Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou: A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. ISCAS (4) 2001: 422-425

Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou: A resonant clock generator for single-phase adiabatic systems. ISLPED 2001: 159-164

Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak: Optimizing computations for effective block-processing. ACM Trans. Design Autom. Electr. Syst. 5(3): 604-630 (2000)

Inki Hong, Darko Kirovski, Miodrag Potkonjak, Marios C. Papaefthymiou: Symbolic debugging of globally optimized behavioral specifications. ASP-DAC 2000: 397-400

Joohee Kim, Marios C. Papaefthymiou: Dynamic Memory Design for Low Data-Retention Power. PATMOS 2000: 207-216

Inki Hong, Miodrag Potkonjak, Marios C. Papaefthymiou: Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors. Design Autom. for Emb. Sys. 4(4): 311-327 (1999)

Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman: Maximizing Performance by Retiming and Clock Skew Scheduling. DAC 1999: 231-236

Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman: Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits. DATE 1999: 643-649

Giuseppe Bernacchia, Marios C. Papaefthymiou: Analytical macromodeling for high-level power estimation. ICCAD 1999: 280-283

Suhwan Kim, Marios C. Papaefthymiou: Single-phase source-coupled adiabatic logic. ISLPED 1999: 97-99

Marios C. Papaefthymiou: Asymptotically efficient retiming under setup and hold constraints. ICCAD 1998: 396-401

Suhwan Kim, Marios C. Papaefthymiou: True single-phase energy-recovering logic for low-power, high-speed VLSI. ISLPED 1998: 167-172

Kumar N. Lalgudi, Marios C. Papaefthymiou: Computing Strictly-Second Shortest Paths. Inf. Process. Lett. 63(4): 177-181 (1997)

Alexander T. Ishii, Charles E. Leiserson, Marios C. Papaefthymiou: Optimizing two-phase, level-clocked circuitry. J. ACM 44(1): 148-199 (1997)

Kumar N. Lalgudi, Marios C. Papaefthymiou: Retiming edge-triggered circuits under general delay models. IEEE Trans. on CAD of Integrated Circuits and Systems 16(12): 1393-1408 (1997)

Fang Wang, Marios C. Papaefthymiou, Mark S. Squillante: Performance Evaluation of Gang Scheduling for Parallel and Distributed Multiprogramming. JSSPP 1997: 277-298

Mark S. Squillante, Fang Wang, Marios C. Papaefthymiou: Stochastic Analysis of Gang Scheduling in Parallel and Distributed Systems. Perform. Eval. 27/28(4): 273-296 (1996)

Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak: Optimizing Systems for Effective Block-Processing: The k-Delay Problem. DAC 1996: 714-719

Marios C. Papaefthymiou, Kumar N. Lalgudi: Fixed-phase retiming for low power design. ISLPED 1996: 259-264

Fang Wang, Hubertus Franke, Marios C. Papaefthymiou, Pratap Pattnaik, Larry Rudolph, Mark S. Squillante: A Gang Scheduling Design for Multiprogrammed Parallel Computing Environments. JSSPP 1996: 111-125

Mark S. Squillante, Fang Wang, Marios C. Papaefthymiou: An Analysis of Gang Scheduling for Multiprogrammed Parallel Computing Environments. SPAA 1996: 89-98

Kumar N. Lalgudi, Marios C. Papaefthymiou: Efficient retiming under a general delay model. ARVLSI 1995: 368-382

Kumar N. Lalgudi, Marios C. Papaefthymiou: DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling. DAC 1995: 304-309

Marios C. Papaefthymiou: Understanding Retiming Through Maximum Avarage-Delay Cycles. Mathematical Systems Theory 27(1): 65-84 (1994)

Mazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou: Precomputation-based sequential logic optimization for low power. IEEE Trans. VLSI Syst. 2(4): 426-436 (1994)

Mazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou: Precomputation-based sequential logic optimization for low power. ICCAD 1994: 74-81

Anant Agarwal, John V. Guttag, Christoforos N. Hadjicostis, Marios C. Papaefthymiou: Memory Assignment for Multiprocessor Caches through Grey Coloring. PARLE 1994: 351-362

Marios C. Papaefthymiou, Keith H. Randall: TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry. DAC 1993: 497-502

Marios C. Papaefthymiou: Understanding Retiming Through Maximum Average-Weight Cycles. SPAA 1991: 338-348