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David Z. Pan
David Zhigang Pan
2010 – today
- 2013
[j35]Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan: Structure-Aware Placement Techniques for Designs With Datapaths. IEEE Trans. on CAD of Integrated Circuits and Systems 32(2): 228-241 (2013)- [j34]Krit Athikulwongse, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim: Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs. IEEE Trans. on CAD of Integrated Circuits and Systems 32(6): 905-917 (2013)
- [j33]Ashutosh Chakraborty, David Z. Pan: Skew Management of NBTI Impacted Gated Clock Trees. IEEE Trans. on CAD of Integrated Circuits and Systems 32(6): 918-927 (2013)
- [j32]Wooyoung Jang, David Z. Pan: Chemical-Mechanical Polishing-Aware Application-Specific 3D NoC Design. IEEE Trans. on CAD of Integrated Circuits and Systems 32(6): 940-951 (2013)
- [c110]Bei Yu, Jhih-Rong Gao, David Z. Pan: L-shape based layout fracturing for e-beam lithography. ASP-DAC 2013: 249-254
- [c109]Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan: Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures. DAC 2013: 48
- [c108]Bei Yu, Kun Yuan, Jhih-Rong Gao, David Z. Pan: E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system. DAC 2013: 70
- [c107]
- 2012
- [j31]Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Gi-Joon Nam, Michael Orshansky, David Z. Pan: An accurate sparse-matrix based framework for statistical static timing analysis. Integration 45(4): 365-375 (2012)
- [j30]Kun Yuan, Bei Yu, David Z. Pan: E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters. IEEE Trans. on CAD of Integrated Circuits and Systems 31(2): 167-179 (2012)
- [j29]Moongon Jung, Joydeep Mitra, David Z. Pan, Sung Kyu Lim: TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC. IEEE Trans. on CAD of Integrated Circuits and Systems 31(8): 1194-1207 (2012)
- [j28]Wooyoung Jang, David Z. Pan: A3MAP: Architecture-aware analytic mapping for networks-on-chip. ACM Trans. Design Autom. Electr. Syst. 17(3): 26 (2012)
- [j27]Ou He, Sheqin Dong, Wooyoung Jang, Jinian Bian, David Z. Pan: UNISM: Unified Scheduling and Mapping for General Networks on Chip. IEEE Trans. VLSI Syst. 20(8): 1496-1509 (2012)
- [c106]Vijay Janapa Reddi, David Z. Pan, Sani R. Nassif, Keith A. Bowman: Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues. ASP-DAC 2012: 7-16
- [c105]Duo Ding, Bei Yu, Joydeep Ghosh, David Z. Pan: EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation. ASP-DAC 2012: 263-270
- [c104]Duo Ding, Bei Yu, David Z. Pan: GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing. ASP-DAC 2012: 621-626
- [c103]David Z. Pan, Sung Kyu Lim, Krit Athikulwongse, Moongon Jung, Joydeep Mitra, Jiwoo Pak, Mohit Pathak, Jae-Seok Yang: Design for manufacturability and reliability for TSV-based 3D ICs. ASP-DAC 2012: 750-755
- [c102]Moongon Jung, David Z. Pan, Sung Kyu Lim: Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs. DAC 2012: 317-326
- [c101]Samuel I. Ward, Duo Ding, David Z. Pan: PADE: a high-performance placer with automatic datapath extraction and evaluation through high dimensional data learning. DAC 2012: 756-761
- [c100]Yen-Hung Lin, Bei Yu, David Z. Pan, Yih-Lang Li: TRIAD: A triple patterning lithography aware detailed router. ICCAD 2012: 123-129
- [c99]Yilin Zhang, Ashutosh Chakraborty, Salim Chowdhury, David Z. Pan: Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree construction. ICCAD 2012: 137-143
- [c98]Bei Yu, Jhih-Rong Gao, Duo Ding, Yongchan Ban, Jae-Seok Yang, Kun Yuan, Minsik Cho, David Z. Pan: Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper). ICCAD 2012: 240-242
- [c97]Jiwoo Pak, Sung Kyu Lim, David Z. Pan: Electromigration-aware routing for 3D ICs with stress-aware EM modeling. ICCAD 2012: 325-332
- [c96]Jhih-Rong Gao, David Z. Pan: Flexible self-aligned double patterning aware detailed routing with prescribed layout planning. ISPD 2012: 25-32
- [c95]Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan: Keep it straight: teaching placement how to better handle designs with datapaths. ISPD 2012: 79-86
- 2011
- [j26]Yongchan Ban, David Z. Pan: Modeling of Layout Aware Line-Edge Roughness and Poly Optimization for Leakage Minimization. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(2): 150-159 (2011)
- [j25]Wooyoung Jang, David Z. Pan: A Voltage-Frequency Island Aware Energy Optimization Framework for Networks-on-Chip. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 420-432 (2011)
- [j24]Anand Rajaram, David Z. Pan: Robust Chip-Level Clock Tree Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 30(6): 877-890 (2011)
- [j23]Wooyoung Jang, David Z. Pan: Application-Aware NoC Design for Efficient SDRAM Access. IEEE Trans. on CAD of Integrated Circuits and Systems 30(10): 1521-1533 (2011)
- [j22]Duo Ding, J. Andres Torres, David Z. Pan: High Performance Lithography Hotspot Detection With Successively Refined Pattern Identifications and Machine Learning. IEEE Trans. on CAD of Integrated Circuits and Systems 30(11): 1621-1634 (2011)
- [c94]Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Thomas Ernst, Olivier Faynot, David Z. Pan, Giovanni De Micheli: CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits. ASP-DAC 2011: 336-343
- [c93]Chul-Hong Park, David Z. Pan, Kevin Lucas: Exploration of VLSI CAD researches for early design rule evaluation. ASP-DAC 2011: 405-406
- [c92]Ashutosh Chakraborty, David Z. Pan: Controlling NBTI degradation during static burn-in testing. ASP-DAC 2011: 597-602
- [c91]Jae-Seok Yang, Jiwoo Pak, Xin Zhao, Sung Kyu Lim, David Z. Pan: Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs. ASP-DAC 2011: 621-626
- [c90]Duo Ding, Andres J. Torres, Fedor G. Pikus, David Z. Pan: High performance lithographic hotspot detection using hierarchically refined machine learning. ASP-DAC 2011: 775-780
- [c89]Moongon Jung, Joydeep Mitra, David Z. Pan, Sung Kyu Lim: TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC. DAC 2011: 188-193
- [c88]Yongchan Ban, Kevin Lucas, David Z. Pan: Flexible 2D layout decomposition framework for spacer-type double pattering lithography. DAC 2011: 789-794
- [c87]Duo Ding, Jhih-Rong Gao, Kun Yuan, David Z. Pan: AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection. DAC 2011: 795-800
- [c86]Bei Yu, Kun Yuan, Boyang Zhang, Duo Ding, David Z. Pan: Layout decomposition for triple patterning lithography. ICCAD 2011: 1-8
- [c85]Wooyoung Jang, Ou He, Jae-Seok Yang, David Z. Pan: Chemical-mechanical polishing aware application-specific 3D NoC design. ICCAD 2011: 207-212
- [c84]Yen-Hung Lin, Yongchan Ban, David Z. Pan, Yih-Lang Li: Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing. ICCAD 2011: 283-289
- [c83]Mohit Pathak, Jiwoo Pak, David Z. Pan, Sung Kyu Lim: Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs. ICCAD 2011: 555-562
- [c82]Moongon Jung, Xi Liu, Suresh K. Sitaraman, David Z. Pan, Sung Kyu Lim: Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC. ICCAD 2011: 563-570
- [c81]
- 2010
- [j21]David Z. Pan, Minsik Cho, Kun Yuan: Manufacturability Aware Routing in Nanometer VLSI. Foundations and Trends in Electronic Design Automation 4(1): 1-97 (2010)
- [j20]Kun Yuan, Jae-Seok Yang, David Z. Pan: Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 185-196 (2010)
- [j19]Ashutosh Chakraborty, Sean X. Shi, David Z. Pan: Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement. IEEE Trans. on CAD of Integrated Circuits and Systems 29(10): 1533-1545 (2010)
- [j18]Wooyoung Jang, David Z. Pan: An SDRAM-Aware Router for Networks-on-Chip. IEEE Trans. on CAD of Integrated Circuits and Systems 29(10): 1572-1585 (2010)
- [j17]Anand Rajaram, David Z. Pan: MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 29(12): 1945-1958 (2010)
- [c80]Wooyoung Jang, David Z. Pan: A3MAP: architecture-aware analytic mapping for networks-on-chip. ASP-DAC 2010: 523-528
- [c79]Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, David Z. Pan: A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography. ASP-DAC 2010: 637-644
- [c78]Yongchan Ban, David Z. Pan: Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography. DAC 2010: 408-411
- [c77]Wooyoung Jang, David Z. Pan: Application-aware NoC design for efficient SDRAM access. DAC 2010: 453-456
- [c76]Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan: TSV stress aware timing analysis with applications to 3D-IC layout optimization. DAC 2010: 803-806
- [c75]Kun Yuan, David Z. Pan: WISDOM: Wire spreading enhanced decomposition of masks in Double Patterning Lithography. ICCAD 2010: 32-38
- [c74]Minsik Cho, David Z. Pan, Ruchir Puri: Novel binary linear programming for high performance clock mesh synthesis. ICCAD 2010: 438-443
- [c73]Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim: Stress-driven 3D-IC placement with TSV keep-out zone and regularity study. ICCAD 2010: 669-674
- [c72]Ashutosh Chakraborty, David Z. Pan: PASAP: power aware structured ASIC placement. ISLPED 2010: 395-400
- [c71]Yongchan Ban, Savithri Sundareswaran, David Z. Pan: Total sensitivity based dfm optimization of standard library cells. ISPD 2010: 113-120
- [c70]Ashutosh Chakraborty, David Z. Pan: Skew management of NBTI impacted gated clock trees. ISPD 2010: 127-133
2000 – 2009
- 2009
- [j16]Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan: ELIAD: Efficient Lithography Aware Detailed Routing Algorithm With Compact and Macro Post-OPC Printability Prediction. IEEE Trans. on CAD of Integrated Circuits and Systems 28(7): 1006-1016 (2009)
- [j15]Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan: BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability. ACM Trans. Design Autom. Electr. Syst. 14(2) (2009)
- [c69]Kun Yuan, Katrina Lu, David Z. Pan: Double patterning lithography friendly detailed routing with redundant via consideration. DAC 2009: 63-66
- [c68]Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen, David Z. Pan: O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration. DAC 2009: 264-269
- [c67]Ashutosh Chakraborty, Anurag Kumar, David Z. Pan: RegPlace: a high quality open-source placement framework for structured ASICs. DAC 2009: 442-447
- [c66]
- [c65]Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan: Analysis and optimization of NBTI induced clock skew in gated clock trees. DATE 2009: 296-299
- [c64]Ashutosh Chakraborty, David Z. Pan: On stress aware active area sizing, gate sizing, and repeater insertion. ISPD 2009: 35-42
- [c63]Kun Yuan, Jae-Seok Yang, David Z. Pan: Double patterning layout decomposition for simultaneous conflict and stitch minimization. ISPD 2009: 107-114
- [c62]
- 2008
- [j14]Patrick H. Madden, David Z. Pan: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 608-609 (2008)
- [j13]Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan: Track Routing and Optimization for Yield. IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 872-882 (2008)
- [j12]Minsik Cho, David Z. Pan: A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips. IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1714-1724 (2008)
- [j11]David Z. Pan, Gi-Joon Nam: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2105-2106 (2008)
- [j10]Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang: Metal-Density-Driven Placement for CMP Variation and Routability. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2145-2155 (2008)
- [j9]Minsik Cho, David Z. Pan: Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs. IEEE Trans. VLSI Syst. 16(12): 1713-1717 (2008)
- [c61]David Z. Pan, Minsik Cho: Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond. ASP-DAC 2008: 220-225
- [c60]Anand Rajaram, David Z. Pan: MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks. ASP-DAC 2008: 250-257
- [c59]Tao Luo, David Z. Pan: DPlace2.0: A stable and efficient analytical placement based on diffusion. ASP-DAC 2008: 346-351
- [c58]Tao Luo, David Newmark, David Z. Pan: Total power optimization combining placement, sizing and multi-Vt through slack distribution management. ASP-DAC 2008: 352-357
- [c57]Peng Yu, Xi Chen, David Z. Pan, Andrew D. Ellington: Synthetic Biology Design and Analysis: A Case Study of Frequency Entrained Biological Clock. BIBM 2008: 329-334
- [c56]Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan: ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction. DAC 2008: 504-509
- [c55]Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan: An integrated nonlinear placement framework with congestion and porosity aware buffer planning. DAC 2008: 702-707
- [c54]Anand Rajaram, David Z. Pan: Robust chip-level clock tree synthesis for SOC designs. DAC 2008: 720-723
- [c53]Ashutosh Chakraborty, Sean X. Shi, David Z. Pan: Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices. DATE 2008: 849-855
- [c52]Sean X. Shi, Anand Ramalingam, Daifeng Wang, David Z. Pan: Latch Modeling for Statistical Timing Analysis. DATE 2008: 1136-1141
- [c51]David Z. Pan, Stephen Renwick, Vivek Singh, Judy Huckabay: Nanolithography and CAD challenges for 32nm/22nm and beyond. ICCAD 2008: 6
- [c50]Tao Luo, David A. Papa, Zhuo Li, Chin Ngai Sze, Charles J. Alpert, David Z. Pan: Pyramids: an efficient computational geometry-based approach for timing-driven placement. ICCAD 2008: 204-211
- [c49]Wooyoung Jang, Duo Ding, David Z. Pan: A voltage-frequency island aware energy optimization framework for networks-on-chip. ICCAD 2008: 264-269
- [c48]Jae-Seok Yang, David Z. Pan: Overlay aware interconnect and timing variation modeling for double patterning technology. ICCAD 2008: 488-493
- [c47]Minsik Cho, Yongchan Ban, David Z. Pan: Double patterning technology friendly detailed routing. ICCAD 2008: 506-511
- [c46]Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang: Metal-density driven placement for cmp variation and routability. ISPD 2008: 31-38
- [c45]Minsik Cho, David Z. Pan: A high-performance droplet router for digital microfluidic biochips. ISPD 2008: 200-206
- [c44]David Z. Pan: Synergistic modeling and optimization for nanometer IC design/manufacturing integration. SBCCI 2008: 2
- [c43]David Z. Pan: Lithography friendly routing: from construct-by-correction to correct-by-construction. SBCCI 2008: 6
- [e2]David Z. Pan, Gi-Joon Nam (Eds.): Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008. ACM 2008, ISBN 978-1-60558-048-7
- 2007
- [j8]Anand Ramalingam, Anirudh Devgan, David Z. Pan: Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce. J. Low Power Electronics 3(1): 28-35 (2007)
- [j7]Minsik Cho, David Z. Pan: BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2130-2143 (2007)
- [j6]Haoxing Ren, David Z. Pan, Charles J. Alpert, Paul G. Villarrubia, Gi-Joon Nam: Diffusion-Based Placement Migration With Application on Legalization. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2158-2172 (2007)
- [c42]Haoxing Ren, David Z. Pan, Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia: Hippocrates: First-Do-No-Harm Detailed Placement. ASP-DAC 2007: 141-146
- [c41]Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan: TROY: Track Router with Yield-driven Wire Planning. DAC 2007: 55-58
- [c40]Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan: Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis. DAC 2007: 148-153
- [c39]Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan: BoxRouter 2.0: architecture and implementation of a hybrid and robust global router. ICCAD 2007: 503-508
- [c38]Peng Yu, David Z. Pan: TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction. ICCAD 2007: 847-853
- [c37]Peng Yu, David Z. Pan: A novel intensity based optical proximity correction algorithm with speedup in lithography simulation. ICCAD 2007: 854-859
- [c36]Anand Ramalingam, Giri Devarayanadurg, David Z. Pan: Accurate power grid analysis with behavioral transistor network modeling. ISPD 2007: 43-50
- [c35]Gi-Joon Nam, Mehmet Can Yildiz, David Z. Pan, Patrick H. Madden: ISPD placement contest updates and ISPD 2007 global routing contest. ISPD 2007: 167
- [c34]Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan: Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis. ISQED 2007: 398-403
- [e1]Patrick H. Madden, David Z. Pan (Eds.): Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007. ACM 2007, ISBN 978-1-59593-613-4
- 2006
- [c33]Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan: Robust analytical gate delay modeling for low voltage circuits. ASP-DAC 2006: 61-66
- [c32]Sean X. Shi, David Z. Pan: Wire sizing with scattering effect for nanoscale interconnection. ASP-DAC 2006: 503-508
- [c31]Minsik Cho, Hongjoong Shin, David Z. Pan: Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs. ASP-DAC 2006: 765-770
- [c30]Minsik Cho, David Z. Pan: BoxRouter: a new global router based on box expansion and progressive ILP. DAC 2006: 373-378
- [c29]Peng Yu, Sean X. Shi, David Z. Pan: Process variation aware OPC with variational lithography modeling. DAC 2006: 785-790
- [c28]Tao Luo, David Newmark, David Z. Pan: A new LP based incremental timing driven placement for high performance designs. DAC 2006: 1115-1120
- [c27]Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan: An accurate sparse matrix based framework for statistical static timing analysis. ICCAD 2006: 231-236
- [c26]Sean X. Shi, Peng Yu, David Z. Pan: A unified non-rectangular device and circuit simulation model for timing and power. ICCAD 2006: 423-428
- [c25]Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri: Wire density driven global routing for CMP variation and timing. ICCAD 2006: 487-492
- [c24]Avijit Dutta, David Z. Pan: Partial Functional Manipulation Based Wirelength Minimization. ICCD 2006
- [c23]Anand Rajaram, David Z. Pan: Variation tolerant buffered clock network synthesis with cross links. ISPD 2006: 157-164
- [c22]Anand Rajaram, David Z. Pan: Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction. ISQED 2006: 79-84
- [c21]Andrew Havlir, David Z. Pan: Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines. ISQED 2006: 171-178
- [c20]Anand Ramalingam, David Z. Pan, Frank Liu, Sani R. Nassif: Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity. ISQED 2006: 644-649
- [c19]
- 2005
- [j5]Haoxing Ren, David Zhigang Pan, David S. Kung: Sensitivity guided net weighting for placement-driven synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 711-721 (2005)
- [c18]Anand Ramalingam, Bin Zhang, Anirudh Devgan, David Z. Pan: Sleep transistor sizing using timing criticality and temporal currents. ASP-DAC 2005: 1094-1097
- [c17]Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wong: CMP aware shuttle mask floorplanning. ASP-DAC 2005: 1111-1114
- [c16]Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. Wong: Redundant-via enhanced maze routing for yield improvement. ASP-DAC 2005: 1148-1151
- [c15]Joydeep Mitra, Peng Yu, David Zhigang Pan: RADAR: RET-aware detailed routing using fast lithography simulations. DAC 2005: 369-372
- [c14]Haoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia: Diffusion-based placement migration. DAC 2005: 515-520
- [c13]Tao Luo, Haoxing Ren, Charles J. Alpert, David Zhigang Pan: Computational geometry based placement migration. ICCAD 2005: 41-47
- [c12]Minsik Cho, Suhail Ahmed, David Z. Pan: TACO: temperature aware clock-tree optimization. ICCAD 2005: 582-587
- [c11]Anand Rajaram, David Z. Pan, Jiang Hu: Improved algorithms for link-based non-tree clock networks for skew variability reduction. ISPD 2005: 55-62
- 2004
- [c10]Haoxing Ren, David Zhigang Pan, Paul Villarrubia: True crosstalk aware incremental placement with noise map. ICCAD 2004: 402-409
- [c9]Haoxing Ren, David Zhigang Pan, David S. Kung: Sensitivity guided net weighting for placement driven synthesis. ISPD 2004: 10-17
- 2003
- [j4]Chin-Chih Chang, Jason Cong, David Zhigang Pan, Xin Yuan: Multilevel global placement with congestion control. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 395-409 (2003)
- [c8]Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni: Pushing ASIC performance in a power envelope. DAC 2003: 788-793
- 2002
- [j3]Jason Cong, David Zhigang Pan: Wire width planning for interconnect performance optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 319-329 (2002)
- [c7]Chin-Chih Chang, Jason Cong, David Zhigang Pan: Physical hierarchy generation with routing congestion control. ISPD 2002: 36-41
- 2001
- [j2]Jason Cong, David Zhigang Pan: Interconnect performance estimation models for design planning. IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 739-752 (2001)
- [j1]Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan: Interconnect sizing and spacing with consideration of couplingcapacitance. IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1164-1169 (2001)
- [c6]Jason Cong, David Zhigang Pan, Prasanna V. Srinivas: Improved crosstalk modeling for noise constrained interconnect optimization. ASP-DAC 2001: 373-378
1990 – 1999
- 1999
- [c5]Jason Cong, David Zhigang Pan: Interconnect Delay Estimation Models for Synthesis and Design Planning. ASP-DAC 1999: 97-100
- [c4]Jason Cong, David Zhigang Pan: Interconnect Estimation and Dlanning for Deep Submicron Designs. DAC 1999: 507-510
- [c3]Jason Cong, Tianming Kong, David Zhigang Pan: Buffer block planning for interconnect-driven floorplanning. ICCAD 1999: 358-363
- 1997
- [c2]Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo: Interconnect design for deep submicron ICs. ICCAD 1997: 478-485
- [c1]Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan: Global interconnect sizing and spacing with consideration of coupling capacitance. ICCAD 1997: 628-633
Coauthor Index
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last updated on 2013-05-29 01:54 CEST by the dblp team