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S. K. Nandy
Soumitra Kumar Nandy
2010 – today
- 2013
[c73]Abhijit Giri, S. K. Nandy: Optimal Pipeline Depth and Supply Voltage for Power-constrained Processors. VLSI Design 2013: 37-42- 2012
- [c72]
- 2011
- [c71]Ratna Krishnamoorthy, Keshavan Varadarajan, Masahiro Fujita, Mythri Alle, S. K. Nandy, Ranjani Narayan: Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture. ARC 2011: 125-132
- [c70]Ratna Krishnamoorthy, Masahiro Fujita, Keshavan Varadarajan, S. K. Nandy: Interconnect-topology independent mapping algorithm for a Coarse Grained Reconfigurable Architecture. FPT 2011: 1-5
- [c69]Adarsha Rao, S. K. Nandy, Hristo Nikolov, Ed F. Deprettere: USHA: Unified software and hardware architecture for video decoding. SASP 2011: 30-37
- [c68]Saptarsi Das, Keshavan Varadarajan, Ganesh Garga, Rajdeep Mondal, Ranjani Narayan, S. K. Nandy: A Method for Flexible Reduction over Binary Fields using a Field Multiplier. SECRYPT 2011: 50-58
- 2010
- [c67]
- [c66]Ratna Krishnamoorthy, Keshavan Varadarajan, Ganesh Garga, Mythri Alle, S. K. Nandy, Ranjani Narayan, Masahiro Fujita: Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE. CASES 2010: 77-86
- [c65]Prasenjit Biswas, Pramod P. Udupa, Rajdeep Mondal, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan: Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform. ISVLSI 2010: 161-166
- [c64]N. Thambi Prashank, M. Prasadarao, Avinaba Dutta, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan: Enhancements for variable N-point streaming FFT/IFFT on REDEFINE, a runtime reconfigurable architecture. ICSAMOS 2010: 178-184
- [c63]Prasenjit Biswas, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan: Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform. ICSAMOS 2010: 265-272
2000 – 2009
- 2009
- [j14]T. Ray Mahapatra, S. K. Nandy, A. S. Gupta: Analytical solution of magnetohydrodynamic stagnation-point flow of a power-law fluid towards a stretching surface. Applied Mathematics and Computation 215(5): 1696-1710 (2009)
- [j13]Mythri Alle, Keshavan Varadarajan, Alexander Fell, C. Ramesh Reddy, Joseph Nimmy, Saptarsi Das, Prasenjit Biswas, Jugantor Chetia, Adarsha Rao, S. K. Nandy, Ranjani Narayan: REDEFINE: Runtime reconfigurable polymorphic ASIC. ACM Trans. Embedded Comput. Syst. 9(2) (2009)
- [c62]Mythri Alle, Keshavan Varadarajan, Alexander Fell, S. K. Nandy, Ranjani Narayan: Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures. ARC 2009: 204-215
- [c61]Adarsha Rao, Mythri Alle, Sainath V, Reyaz Shaik, Rajashekhar Chowhan, S. Sankaraiah, Sravanthi Mantha, S. K. Nandy, Ranjani Narayan: An Input Triggered Polymorphic ASIC for H.264 Decoding. ASAP 2009: 106-113
- [c60]Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan: Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. CASES 2009: 127-136
- [c59]J. Lakshmi, S. K. Nandy: I/O Device Virtualization in the Multi-core era, a QoS Perspective. GPC Workshops 2009: 128-135
- [c58]Ritesh Rajore, S. K. Nandy, H. S. Jamadagni: Architecture of Run-Time Reconfigurable Channel Decoder. ICC 2009: 1-6
- [c57]A. N. Satrawala, S. K. Nandy: RETHROTTLE: Execution throttling in the REDEFINE SoC architecture. ICSAMOS 2009: 82-91
- [c56]Ganesh Garga, David Guevorkian, S. K. Nandy, H. S. Jamadagni: High-throughput flexible constraint length Viterbi decoders on de Bruijn, shuffle-exchange and butterfly connected architectures. ICSAMOS 2009: 157-164
- [c55]Alexander Fell, Prasenjit Biswas, Jugantor Chetia, S. K. Nandy, Ranjani Narayan: Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT. SoCC 2009: 251-254
- 2008
- [j12]Subhasis Banerjee, G. Surendra, S. K. Nandy: On the effectiveness of phase based regression models to trade power and performance using dynamic processor adaptation. Journal of Systems Architecture - Embedded Systems Design 54(8): 797-815 (2008)
- [c54]Mythri Alle, Keshavan Varadarajan, Ramesh C. Ramesh, Joseph Nimmy, Alexander Fell, Adarsha Rao, S. K. Nandy, Ranjani Narayan: Synthesis of application accelerators on Runtime Reconfigurable Hardware. ASAP 2008: 13-18
- [c53]Ritesh Rajore, Ganesh Garga, H. S. Jamadagni, S. K. Nandy: Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture. ASAP 2008: 49-54
- [c52]Joseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy, Ranjani Narayan: RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router. ASAP 2008: 251-256
- [c51]Adarsha Rao, Mythri Alle, S. K. Nandy, Ranjani Narayan: Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders. ASAP 2008: 287-292
- 2007
- [j11]Arasu T. Senthil, C. P. Ravikumar, S. K. Nandy: Low-Power Hierarchical Scan Test for Multiple Clock Domains. J. Low Power Electronics 3(1): 106-118 (2007)
- [c50]Subhasis Banerjee, G. Surendra, S. K. Nandy: Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency. ASP-DAC 2007: 884-889
- [c49]A. N. Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan: REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures. FPL 2007: 558-561
- 2006
- [j10]G. Surendra, Subhasis Banerjee, S. K. Nandy: Instruction Reuse in SPEC, media and packet processing benchmarks: A comparative study of power, performance and related microarchitectural optimizations. J. Embedded Computing 2(1): 15-34 (2006)
- [c48]Raghu Anantharangachar, Gorur N. Shrinivas, S. K. Nandy: Towards Self-Composing, Prioritized and Consequential Services. IEEE SCC 2006: 518
- [c47]K. Kalapriya, S. K. Nandy, Nanjangud C. Narendra: A Framework for Measurement of End-To-End Qos Requirements in Loosely Coupled Systems. AINA (2) 2006: 926
- [c46]Sandeep B. Singh, Jayanta Biswas, S. K. Nandy: A Cost Effective Pipelined Divider for Double Precision Floating Point Number. ASAP 2006: 132-137
- [c45]Mythri Alle, Jayanta Biswas, S. K. Nandy: High Performance VLSI Architecture Design for H.264 CAVLC Decoder. ASAP 2006: 317-322
- [c44]Jayanta Biswas, Soumitra Kumar Nandy: Efficient Key Management and Distribution for MANET. ICC 2006: 2256-2261
- [c43]K. Kalapriya, S. K. Nandy: On the Implementation of a Streaming Video over Peer to Peer network using Middleware Components. ICN/ICONS/MCL 2006: 59
- [c42]J. Lakshmi, S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan: Framework for Enabling Highly Available Distributed Applications for Utility Computing. ISPA 2006: 549-560
- [c41]Keshavan Varadarajan, S. K. Nandy, Vishal Sharda, Bharadwaj Amrutur, Ravi R. Iyer, Srihari Makineni, Donald Newell: Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions. MICRO 2006: 433-442
- 2005
- [c40]K. Kalapriya, S. K. Nandy: Throughput Driven, Highly Available Streaming Stored Playback Video Service over a Peer-to-Peer Network. AINA 2005: 229-234
- [c39]K. C. Nainwal, J. Lakshmi, S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan: A Framework for QoS Adaptive Grid Meta Scheduling. DEXA Workshops 2005: 292-296
- [c38]Arasu T. Senthil, C. P. Ravikumar, Soumitra Kumar Nandy: A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer. ITC 2005: 9
- [c37]Nanjangud C. Narendra, Umesh Bellur, S. K. Nandy, K. Kalapriya: Functional and architectural adaptation in pervasive computing environments. MPAC 2005: 1-7
- 2004
- [j9]H. Sarojadevi, S. K. Nandy, S. Balakrishnan: On the Correctness of Program Execution When Cache Coherence Is Maintained Locally at Data-Sharing Boundaries in Distributed Shared Memory Multiprocessors. International Journal of Parallel Programming 32(5): 415-446 (2004)
- [c36]K. Kalapriya, S. K. Nandy, K. Venkatesh Babu: Can Streaming Of Stored Playback Video Be Supported On Peer to Peer Infrastructure? AINA (2) 2004: 200-203
- [c35]G. Surendra, Subhasis Banerjee, S. K. Nandy: Power-performance trade-off using pipeline delays. ASP-DAC 2004: 384-386
- [c34]Subhasis Banerjee, G. Surendra, S. K. Nandy: Exploiting program execution phases to trade power and performance for media workload. ASP-DAC 2004: 387-389
- [c33]K. Kalapriya, S. K. Nandy, Deepti Srinivasan, R. Uma Maheshwari, V. Satish: A framework for resource discovery in pervasive computing for mobile aware task execution. Conf. Computing Frontiers 2004: 70-77
- [c32]K. Kalapriya, S. K. Nandy, V. Satish, R. Uma Maheshwari, Deepti Srinivas: An Architectural View of the Entities Required for Execution of Task in Pervasive Space. FTDCS 2004: 37-43
- [c31]K. Kalapriya, K. Venkatesh Babu, Soumitra Kumar Nandy: Streaming stored playback video over a peer-to-peer network. ICC 2004: 1298-1302
- [c30]G. Surendra, Subhasis Banerjee, S. K. Nandy: On the effectiveness of prefetching and reuse in reducing L1 data cache traffic: a case study of Snort. WMPI 2004: 88-95
- 2003
- [j8]G. Surendra, Subhasis Banerjee, S. K. Nandy: On the Effectiveness of Flow Aggregation in Improving Instruction Reuse in Network Processing Applications. International Journal of Parallel Programming 31(6): 469-487 (2003)
- [c29]Pradeep Rao, S. K. Nandy, M. N. V. Satya Kiran: Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures. Asia-Pacific Computer Systems Architecture Conference 2003: 166-179
- [c28]M. N. V. Satya Kiran, M. N. Jayram, Pradeep Rao, S. K. Nandy: A complexity effective communication model for behavioral modeling of signal processing applications. DAC 2003: 412-415
- [c27]G. Surendra, Subhasis Banerjee, S. K. Nandy: Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation. DATE 2003: 10784-10789
- [c26]K. Kalapriya, B. R. Raghucharan, Abhijit M. Lele, S. K. Nandy: Traffic Profiling for Efficient Network Resource Utilization. International Conference on Internet Computing 2003: 789-795
- [c25]Amitabh Menon, S. K. Nandy, Mahesh Mehendale: Multivoltage scheduling with voltage-partitioned variable storage. ISLPED 2003: 298-301
- 2002
- [c24]H. Sarojadevi, S. K. Nandy, S. Balakrishnan: Enforcing Cache Coherence at Data Sharing Boundaries without Global Control: A Hardware-Software Approach (Research Note). Euro-Par 2002: 543-546
- [c23]Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhoven, S. Balakrishnan: Speculative Trace Scheduling in VLIW Processors. ICCD 2002: 408-413
- [c22]Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhoven, S. Balakrishnan: On the Benefits of Speculative Trace Scheduling in VLIW Processors. PDPTA 2002: 822-828
- 2001
- [c21]A. Ahmed, S. K. Nandy, Paul Sathya: Content adaptive motion estimation for mobile video encoders. ISCAS (2) 2001: 237-240
- [c20]G. Surendra, S. K. Nandy, Paul Sathya: ReDeEm_RTL: A Software Tool for Customizing Soft Cells for Embedded Applications. VLSI Design 2001: 85-90
- [c19]Abhijit M. Lele, S. K. Nandy: Architecture of Reconfigurable a Low Power Gigabit AT Switch. VLSI Design 2001: 242-247
- 2000
- [j7]Abhijit M. Lele, S. K. Nandy, Dick H. J. Epema: Harmony - An Architecture for Providing Quality of Service in Mobile Computing Environments. Journal of Interconnection Networks 1(3): 247-266 (2000)
- [j6]S. Ramanathan, S. K. Nandy, V. Visvanathan: Reconfigurable Filter Coprocessor Architecture for DSP Applications. VLSI Signal Processing 26(3): 333-359 (2000)
- [c18]
- [c17]Abhijit M. Lele, S. K. Nandy, Dick H. J. Epema: Design Space Exploration for Orividing QoS Within the Harmony Framework. IEEE International Conference on Multimedia and Expo (I) 2000: 521-524
1990 – 1999
- 1999
- [j5]S. Ramanathan, V. Visvanathan, S. K. Nandy: Synthesis of ASIPs for DSP algorithms. Integration 28(1): 13-32 (1999)
- [j4]S. Ramanathan, V. Visvanathan, S. K. Nandy: A computational engine for multirate FIR digital filtering. Signal Processing 79(2): 213-222 (1999)
- [j3]S. Ramanathan, V. Visvanathan, S. K. Nandy: Architectural Synthesis of Computational Engines for Subband Adaptive Filtering. VLSI Signal Processing 22(3): 173-195 (1999)
- [c16]Abhijit M. Lele, S. K. Nandy: Harmony - A Framework for Providing Quality of Service in Wireless Mobile Computing Environment. HiPC 1999: 299-308
- [c15]Avinash K. Gautam, V. Visvanathan, S. K. Nandy: Automatic Generation of Tree Multipliers Using Placement-Driven Netlists. ICCD 1999: 285-288
- [c14]S. Ramanathan, V. Visvanathan, S. K. Nandy: Synthesis of Configurable Architectures for DSP Algorithms. VLSI Design 1999: 350-357
- 1998
- [c13]S. Balakrishnan, Soumitra Kumar Nandy: Arbitrary Precision Arithmetic - SIMD Style. VLSI Design 1998: 128-132
- 1997
- [j2]Vinod Menezes, S. K. Nandy, Biswadip Mitra: Signal compression through spatial frequency-based motion estimation. Integration 22(1-2): 115-135 (1997)
- [c12]M. R. Karthikeyan, Soumitra Kumar Nandy: An asynchronous architecture for digital signal processors. ED&TC 1997: 615
- 1995
- [j1]Debabrata Ghosh, S. K. Nandy: Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology. IEEE Trans. VLSI Syst. 3(1): 36-48 (1995)
- [c11]Debabrata Ghosh, Soumitra Kumar Nandy: Wave pipelined architecture folding: a method to achieve low power and low area. VLSI Design 1995: 184-
- 1994
- [c10]Debabrata Ghosh, S. K. Nandy, K. Parthasarathy: TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor. VLSI Design 1994: 77-82
- [c9]Debabrata Ghosh, Shamik Sural, S. K. Nandy: A 600MHz Half-Bit Level Pipelined Multiplier Macrocell. VLSI Design 1994: 95-100
- [c8]G. N. Rathna, S. K. Nandy, K. Parthasarathy: A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs. VLSI Design 1994: 225-228
- [c7]Abhijit Giri, V. Visvanathan, S. K. Nandy, S. K. Ghoshal: High Speed Digital Filtering on SRAM-Based FPGAs. VLSI Design 1994: 229-232
- 1993
- [c6]Debabrata Ghosh, S. K. Nandy, P. Sadayappan, K. Parthasarathy: Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving. DAC 1993: 303-307
- [c5]Debabrata Ghosh, S. K. Nandy: A 400 MHz Wave-Pipelined 8 X 8-Bit Multiplier in CMOS Technology. ICCD 1993: 198-201
- [c4]S. K. Nandy, Ranjani Narayan, V. Visvanathan, P. Sadayappan, Prashant S. Chauhan: A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array. ICPP 1993: 94-97
- [c3]Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan: NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. VLSI Design 1993: 341-346
1980 – 1989
- 1989
- [c2]Narasimha B. Bhat, S. K. Nandy: Special Purpose Architecture for Accelerating Bitmap DRC. DAC 1989: 674-677
- 1986
- [c1]
Coauthor Index
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last updated on 2013-03-15 01:12 CET by the dblp team